CY28RS400
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
Description
Description
Description
7
1
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC [T/C]0
SRCS[T/C]1
SRCS[T/C]0
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
7
1
REF2
REF2 Output Enable
0 = Disable, 1 = Enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
REF1
REF0
REF1 Output Enable
0 = Disable, 1 = Enable
REF0 Output Enable
0 = Disable, 1 = Enable
PCI0
PCI0 Output Enable
0 = Disable, 1 = Enable
USB_48
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
USB_48MHz Output Enable
0 = Disable, 1 = Enable
CPU[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 2: Control Register 2
Bit
@Pup
Name
7
1
CPUT/C
SRCT/C
Spread Spectrum Selection
‘0’ = -0.35%
‘1’ = -0.50%
6
5
1
1
USB_48
PCI
48MHz Output Drive Strength
0 = 1x, 1 = 2x
33MHz Output Drive Strength
0 = 1x, 1 = 2x
4
3
2
0
1
0
Reserved
Reserved
Reserved
Reserved
CPU
SRC
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
1
1
Reserved
Reserved
Rev 1.0,November 22, 2006
Page 5 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
