PRELIMINARY
CY28447
Clock Generator for Intel Calistoga Chipset
Features
• Compliant to Intel
®
CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clock
• SRC clocks independently stoppable through
CLKREQ#[1:9]
• 96/100 MHz spreadable differential video clock
CPU
x2 / x3
SRC
x9/11
PCI
x5
REF
x2
DOT96
x1
USB_48M
x1
LCD
x1
27M
x2
• 33 MHz PCI clocks
• Buffered Reference Clock 14.318MHz
• Low-voltage frequency select inputs
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
Block Diagram
XIN
XOUT
SEL_CLKREQ
PCI_STP#
CPU_STP#
CLKREQ[1:9]#
ITP_SEL
FS[C:A]
14.318M
Hz
Crystal
VDD
REF[1:0]
IREF
VDD
CPUT[0:1]
CPUC[0:1]
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD
SRCT(1:9])
SRCC(1:9])
VDD
PCI[1:4]
VDD_PCI
PCIF0
VDD
SRCT0/100M
T_SST
SRCC0/100M
C_SST
VDD48
27MSpread
VDD48
DOT96T
DOT96C
VDD48
48M
27M
PLL
VTT_PW
RGD#/PD
SDATA
SCLK
I2C
Logic
Pin Configuration
CLKREQ9#
CLKREQ8#
SRCT_8
SRCC_8
VSS_SRC
SRCC_7
SRCT_7
VDD_SRC
SRCC_6
SRCT_6
CLKREQ6#
SCRC_5
SRCT_5
SCRC_4
SRCT_4
CLKREQ4#
SRCC_3
SRCT_3
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
PLL Reference
CPU
PLL
Divider
LVDS
PLL
FCTSEL1
Divider
VDD_SRC
SRCC_9
SRCT_9
VSS_SRC
CPUC2_ITP / SRCC_10
CPUT2_ITP / SRCT_10
VDDA
VSSA
IREF
CPUC1
CPUT1
VDD_CPU
CPUC0
CPUT0
VSS_CPU
SCLK
SDATA
VDD_REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54
53
52
51
50
49
48
47
CY28447
46
45
44
43
42
41
40
39
38
37
VDD_SRC
SRCC_2
SRCT_2
SRCC_1
SRCT_1
VDD_SRC
SRCC_0 / LCD100MC
SRCT_0 / LCD100MT
CLKREQ1#
FSB/TEST_MODE
DOT96C / 27M_SS
DOT96T / 27M_NSS
VSS_48
48M / FSA
VDD_48
VTT_PWRGD# / PD
CLKREQ7#
PCIF0/ITP_SEL
Divider
Divider
VDD48
27MNon-spread
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
XOUT
XIN
VSS_REF
REF1
REF0 / FSC_TEST_SEL
CPU_STP#
PCI_STP#
CLKREQ2#
PCI1
CLKREQ3#
CLKREQ5#
VDD_PCI
VSS_PCI
PCI2
PCI3
PCI4 / FCTSEL1
VSS_PCI
VDD_PCI
Fixed
PLL
Page 1 of 21
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