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CY28439OXCT 参数 Datasheet PDF下载

CY28439OXCT图片预览
型号: CY28439OXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为英特尔的Grantsdale芯片组 [Clock Generator for Intel Grantsdale Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 21 页 / 192 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28439  
Byte 2: Control Register 2 (continued)  
Bit  
@Pup  
Name  
Description  
Description  
0
1
PCIF1  
PCIF1 Output Enable  
0 = Disabled, 1 = Enabled  
Byte 3: Control Register 3  
Bit  
7
@Pup  
Name  
RESERVED  
SRC4  
0
0
RESERVED, Set = 0  
6
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
5
4
3
2
0
0
0
0
SRC3  
SATA[T/C]  
SRC2  
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
Allow control of SATA[T/C] with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
SRC1  
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
1
0
0
0
RESERVED  
SRC0  
RESERVED  
Allow control of SRC[T/C]0 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
Byte 4: Control Register 4  
Bit  
@Pup  
Name  
Description  
7
HW  
FS_E  
FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E  
was low during VTT_PWRGD# assertion.  
6
5
4
3
0
0
0
0
DOT96[T/C]  
PCIF2  
DOT_PWRDWN Drive Mode  
0 = Driven in PWRDWN, 1 = Tri-state  
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
PCIF1  
Allow control of PCIF1 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
PCIF0  
Allow control of PCIF0 with assertion of SW PCI_STP#  
0 = Free running, 1 = Stopped with PCI_STP#  
2
1
0
1
1
1
RESERVED  
RESERVED  
RESERVED  
RESERVED, Set = 1  
RESERVED, Set = 1  
RESERVED, Set = 1  
Byte 5: Control Register 5  
Bit  
@Pup  
Name  
Description  
7
0
SRC[T/C]  
SRC[T/C] Stop Drive Mode  
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#  
asserted  
6
5
4
3
0
0
0
0
RESERVED  
RESERVED  
RESERVED  
SRC[T/C][4:0]  
RESERVED, Set = 0  
RESERVED, Set = 0  
RESERVED, Set = 0  
SRC[T/C] PWRDWN Drive Mode  
0 = Driven when PD asserted,1 = Tri-state when PD asserted  
2
1
0
0
RESERVED  
CPU[T/C]1  
RESERVED, Set = 0  
CPU[T/C]1 PWRDWN Drive Mode  
0 = Driven when PD asserted,1 = Tri-state when PD asserted  
0
0
CPU[T/C]0  
CPU[T/C]0 PWRDWN Drive Mode  
0 = Driven when PD asserted,1 = Tri-state when PD asserted  
Rev 1.0,November 21, 2006  
Page 6 of 21