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CY28439OXCT 参数 Datasheet PDF下载

CY28439OXCT图片预览
型号: CY28439OXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为英特尔的Grantsdale芯片组 [Clock Generator for Intel Grantsdale Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 21 页 / 192 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28439  
Byte 12: Control Register 12  
Bit  
7
@Pup  
Name  
Description  
0
0
0
0
0
0
0
0
CPU_DAF_N8  
CPU_DAF_M6  
CPU_DAF_M5  
CPU_DAF_M4  
CPU_DAF_M3  
CPU_DAF_M2  
CPU_DAF_M1  
CPU_DAF_M0  
If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0]  
and CPU_FSEL_M[6:0] will be used to determine the CPU output  
frequency.  
6
5
The setting of FS_Override bit determines the frequency ratio for CPU and  
other output clocks. When it is cleared, the same frequency ratio stated in  
the Latched FS[E:A] register will be used. When it is set, the frequency  
ratio stated in the FSEL[3:0] register will be used.  
4
3
2
1
0
Byte 13: Control Register 13  
Bit  
7
@Pup  
Name  
Description  
SRC Dial-A-Frequency Bit N7  
SRC Dial-A-Frequency Bit N6  
SRC Dial-A-Frequency Bit N5  
SRC Dial-A-Frequency Bit N4  
SRC Dial-A-Frequency Bit N3  
SRC Dial-A-Frequency Bit N2  
SRC Dial-A-Frequency Bit N1  
SRC Dial-A-Frequency Bit N0  
0
0
0
0
0
0
0
0
SRC_N7  
SRC_N6  
SRC_N5  
SRC_N4  
SRC_N3  
SRC_N2  
SRC_N1  
SRC_N0  
6
5
4
3
2
1
0
Byte 14: Control Register 14  
Bit  
7
@Pup  
Name  
SRC_N8  
Description  
0
0
SRC Dial-A-Frequency Bit N8  
6
SW_RESET  
Software Reset.  
When set the device will assert a reset signal on SRESET# upon  
completion of the block/word/byte write that set it. After asserting and  
deasserting the SRESET# this bit will self clear (set to 0).  
The SRESET# pin must be enabled by latching SRESET#_EN on  
VTT_PRWGD# to utilize this feature.  
5
4
0
0
FS_[E:A]  
FS_Override  
0 = Select operating frequency by FS(E:A) input pins  
1 = Select operating frequency by FSEL_(4:0) settings  
SMSW_SEL  
Smooth switch select  
0: Select CPU_PLL  
1: Select SRC_PLL.  
3
2
0
0
RESERVED  
RESERVED  
RESERVED, Set = 0  
RESERVED, Set = 0  
1
0
1
0
PCIF  
Free running 33-MHz Output Drive Strength  
0 = 2x, 1 = 1x  
Recovery_N8  
Watchdog Recovery Bit  
Byte 15: Control Register 15  
Bit  
7
@Pup  
Name  
Description  
Watchdog Recovery Bit  
0
0
0
0
0
Recovery N7  
Recovery N6  
Recovery N5  
Recovery N4  
Recovery N3  
6
Watchdog Recovery Bit  
5
Watchdog Recovery Bit  
4
Watchdog Recovery Bit  
3
Watchdog Recovery Bit  
Rev 1.0,November 21, 2006  
Page 9 of 21