CY28342
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Description
Bit
Description
Bit
30:37
38
Data byte from slave – 8 bits
Not acknowledge
Stop
39
Since SDR and DDR Zero Delay Buffers will share this same address, the device starts from Byte 4.
Byte 4: CPU Clock Register (All bits are Read and Write functional)
Bit
7
@Pup
H/W Setting
H/W Setting
H/W Setting
H/W Setting
0
Pin#
14
4
Name
FS3
FS2
FS1
FS0
Description
For selecting frequencies in Table 1.
For selecting frequencies in Table 1.
For selecting frequencies in Table 1.
For selecting frequencies in Table 1.
0 = HW, 1 = SW frequency selection.
For selecting frequencies in Table 1.
6
5
3
4
2
3
2
H/W Setting
15
FS4
Spread Spectrum Enable. 0 = spread off, 1 = spread on.
This is a Read and Write control bit.
1
0
1
0
SSCG
Master output control 0 = running, 1 = three-state all outputs.
Byte 5: CPU Clock Register (all bits are Read-only)
Bit
@Pup
Pin#
Name
Description
7
0
Reserved.
Reserved.
6
5
4
3
2
1
0
0
X
X
X
X
X
X
26
15
14
4
MULT0
FS4
MULT0 (pin 26) value. This bit is Read-only.
FS4 Read-back. This bit is Read-only.
FS3 Read-back. This bit is Read-only.
FS2 Read-back. This bit is Read-only.
FS1 Read-back. This bit is Read-only.
FS0 Read-back. This bit is Read-only.
FS3
FS2
3
FS1
2
FS0
Byte 6: CPU Clock Register (All bits are Read and Write functional)
Bit @Pup Pin# Name
Description
Function Test Bit. Always program to 0.
Reserved.
7
6
5
4
0
0
0
0
14
15
PCI_F0 PCI_STP# control of PCI_F0. 0 = free running, 1 = stopped when PCI_STP# is LOW.
PCI_F1 PCI_STP# control of PCI_F1. 0 = free running, 1 = stopped when PCI_STP# is LOW.
Controls CPU0T and CPU0C functionality when CPU_STP# is asserted LOW.
3
2
1
0
40,39 CPU0T/C 0 = free running, 1 = stopped with CPU_STP# asserted LOW.
This is a Read and Write control bit.
Controls CPU1T and CPU1C functionality when CPU_STP# is asserted LOW
44,43 CPU1T/C 0= Free Running, 1 Stopped with CPU_STP# asserted to LOW.
This and Read and Write control bit.
CPU0T, CPU0C output control, 1= enabled, 0 = disabled.
40,39 CPU0T/C
1
0
1
1
This is a Read and Write control bit.
CPU1T, CPU1C output control, 1= enabled, 0 = disabled.
44,43 CPU1T/C
This is a Read and Write control bit.
Rev 1.0,November 20, 2006
Page 6 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
