CY28342
Pin Description (continued)[2]
Pin
47
Name
SDCLK
AGP (0:1)
VDDSD
VDDAGP
VDDZ
PWR
I/O
O
Description
VDDSD
VDDAGP
SDRAM Clock Output.
AGP Clock Outputs. See Table 1 for frequencies and functionality.
30,31
48
O
PWR 3.3V power supply for SDRAM clock output.
PWR 3.3V power supply for AGP clock output.
PWR 3.3V power supply for HyperZip clock output.
PWR 3.3V power supply for REF clock output.
PWR 3.3V power supply for PCI clock output.
PWR 3.3V power supply for CPU clock output.
PWR 3.3V power supply for 48-MHz/24-MHz clock output.
PWR 3.3V analog power supply.
29
11
1
VDDR
13,19
42
VDDP
VDDC
28
VDD48M
VDDA
36
18,24
41
VSSP
PWR GND for PCI clocks outputs.
VSSC
PWR GND for CPU clocks outputs.
8
VSSZ
PWR GND for HyperZip clocks outputs.
PWR GND for 48-MHz/24-MHz clocks outputs.
PWR GND for REF clocks outputs.
25
VSS48M
VSSR
5
46
VSSSD
VSSAGP
VSSA
PWR GND for SDRAM clocks outputs.
PWR GND for AGP clocks outputs.
32
37
PWR GND for analog.
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface (SDI), various device functions such as
individual clock output buffers, etc., can be individually
enabled or disabled.
The clock driver serial protocol accepts byte Write, byte Read,
block Write, and block Read operations from the controller. For
a block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte Write and byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The registers associated with the SDI initializes to their default
setting upon power-up, and therefore the use of this interface
is optional. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power
management functions.
The block Write and block Read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte Write and byte
Read protocol.
The slave receiver address is 11010010 (D2h).
Note:
2. PU = Internal pull-up. PD = internal pull-down. T = Tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 –1.8V, and HIGH = > 2.0V.
Rev 1.0,November 20, 2006
Page 4 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
