CY28342
Byte 12: Watchdog Time Stamp Register (All bits are Read and Write functional)
Bit
@Pup
Name
Description
SRESET#/PCI_STP#. 1 = pin 12 is the input pin as PCI_STP# signal. 0 = pin 12 is the output pin
as SRESET# signal.
7
1
Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due
to Watchdog time-out only. 0 = selects frequency of existing H/W setting. 1 = selects frequency of
the second to last S/W setting (the software setting prior to the one that caused a system reboot).
6
0
5
4
0
0
WDTEST. For WD-Test, ALWAYS program to “0.”
WD Alarm. This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system
clears the WD time stamps (WD3:0).
3
2
1
0
0
0
0
0
WD3 These bits select the Watchdog Time Stamp Value. See Table 8.
WD2
WD1
WD0
Table 8. Watchdog Time Stamp Table
WD(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FUNCTION
Off
1 second
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
Byte 13: Dial-a-Frequency Control Register N (All bits are Read and Write functional)[5]
Bit
7
@Pup
Description
0
0
0
0
0
0
0
0
Reserved.
N6, MSB
N5
6
5
4
N4
3
N3
2
N2
1
N3
0
N0, LSB
Note:
5. Byte 13 and Byte 14 should be Write together in every case.
Rev 1.0,November 20, 2006
Page 9 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
