CY28341-2
Byte 7: Dial-a-Frequency Control Register N
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reserved
N6, MSB
N5
Reserved for device function test.
These bits are for programming the PLL’s internal N register. This access
allows the user to modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks (clocks that are generated from
the same PLL, such as PCI) remain at their existing ratios relative to the
CPU clock.
N4
N3
N2
N3
N0, LSB
Byte 8: Silicon Signature Register (all bits are read-only)
Bit
7
@Pup
Pin#
Name
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor_ID1
Vendor_ID0
Description
0
0
0
1
1
0
0
0
Revision ID bit [3]
6
Revision ID bit [2]
5
Revision ID bit [1]
4
Revision ID bit [0]
3
Cypress's Vendor ID bit [3].
Cypress's Vendor ID bit [2].
Cypress's Vendor ID bit [1].
Cypress's Vendor ID bit [0].
2
1
0
Byte9: Dial-A-Frequency Control Register R
Bit
7
@Pup
Pin#
Name
Description
0
0
0
0
0
0
0
Reserved
6
R5, MSB
These bits are for programming the PLL’s internal R register. This access
allows the user to modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks (clocks that are generated from
the same PLL, such as PCI) remain at their existing ratios relative to the
CPU clock.
5
R4
R3
R2
R1
R0
4
3
2
1
R and N register mux selection. 0 = R and N values come from the ROM.
1 = data is load from DAF (SMBus) registers.
0
0
DAF_ENB
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via
Byte7 and Byte9.
P is a PLL constant that depends on the frequency selection
prior to accessing the Dial-a-Frequency feature.
Table 8.
FS(4:0)
P
XXXXX
96016000
Rev 1.0,November 21, 2006
Page 8 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
