CY28341-2
Byte 2: PCI Clock Register
Bit
7
@Pup
Pin#
Name
PCI_DRV
Description
0
1
1
1
1
1
1
1
PCI clock output drive strength 0 = Low strength, 1 = High strength
6
10
18
17
15
14
12
11
PCI_F
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
5
4
3
2
1
0
Byte 3: AGP/Peripheral Clocks Register
Bit
@Pup
Pin#
Name
24_48M
Description
0 = pin21 output is 24 MHz. Writing a '1' into this register asynchronously
changes the frequency at pin21 to 48 MHz.
7
0
21
6
5
4
3
2
1
0
1
1
0
0
1
1
1
20
21
48MHz
24_48M
DASAG1
DASAG0
AGP2
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
6,7,8
6,7,8
8
Programming these bits allow shifting skew of the AGP(0:2) signals relative to
their default value. See Table 5.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
7
AGP1
6
AGP0
Table 5. Dial-a-Skew¥ AGP(0:2)
DASAG (1:0)
AGP(0:2) Skew Shift
00
01
10
11
Default
–280 ps
+280 ps
+480 ps
Byte 4: Peripheral Clocks Register
Bit
@Pup
Pin#
Name
Description
1 = Low strength, 0 = High strength
1 = strength x 1. 0= strength x 2
7
1
20
48M
6
1
21
24_48M
1 = Low strength, 0 = High strength
1 = strength x 1. 0= strength x 2
5
4
3
2
1
0
0
0
1
1
1
1
6,7,8
6,7,8
1
DARAG1
DARAG0
REF0
Programming these bits allow modifying the frequency ratio of the AGP(2:0),
PCI(6:1, F) clocks relative to the CPU clocks. See Table 6.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Low strength, 0 = High strength
56
REF1
1
REF0
56
REF1
1 = Low strength, 0 = High strength (K7 Mode only)
Table 6. Dial-A-Ratio¥ AGP(0:2)
DARAG (1:0)
CU/AGP Ratio
00
01
10
11
Frequency Selection Default
2/1
2.5/1
3/1
Rev 1.0,November 21, 2006
Page 6 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
