CY28341-2
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write
2:8
9
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
CommandCode – 8-bit‘1xxxxxxx’ standsforbyte
operationbit[6:0] of the command code repre-
sents the offset of the byte to be accessed
11:18
Command Code – 8-bit ‘1xxxxxxx’ stands for byte
operationbit[6:0] of the command code repre-
sents the offset of the byte to be accessed
19
Acknowledge from slave
19
20
Acknowledge from slave
Repeat start
20:27 Byte Count – 8 bits
28
29
Acknowledge from slave
stop
21:27
28
Slave address – 7 bits
Read
29
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
stop
30:37
38
39
Serial Control Registers
Byte 0: Frequency Select Register
Bit
7
@Pup
0
Pin#
Name
Reserved
FS2
Description
Reserved
6
H/W Setting
H/W Setting
H/W Setting
0
21
10
1
For Selecting Frequencies in Frequency Selection Table on page 1
For Selecting Frequencies in Frequency Selection Table on page 1
For Selecting Frequencies in Frequency Selection Table on page 1
5
FS1
4
FS0
3
If this bit is programmed to “1”, it enables WRITE to bits (6:4,1) for
selecting the frequency via software (SMBus)
If this bit is programmed to a “0” it enable only READ of bits (6:4,1),
which reflect the hardware setting of FS(0:3).
2
H/W Setting
11
SELSDR_DDR Only for reading the hardware setting of the SDRAM interface mode,
status of SELSDR_DDR# strapping.
1
0
H/W Setting
H/W Setting
20
7
FS3
For Selecting frequencies in Frequency Selection Table on page 1
SELP4_K7
Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
Byte 1: CPU Clocks Register
Bit @Pup Pin#
Name
Description
7
6
5
4
3
0
1
1
1
1
MODE
SSCG
SST1
SST0
0 = Down Spread. 1 = Center Spread. See Table 9 on page 9
1 = Enable (default). 0 = Disable
Select spread bandwidth. See Table 9 on page 9
Select spread bandwidth. See Table 9 on page 9
48,49 CPUCS_T, CPUCS_C
1 = Output enabled (running). 0 = Output disabled asynchronously in a low
state.
2
1
1
1
53,52 CPUT/CPUOD_T
CPUC/CPUOD_C
1 = Output enabled (running). 0 = Output disable.
53,52 CPUT/C
In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW,
CPUT stops in a high state, CPUC stops in a low state. In P4 mode, 1 = when
PD# asserted LOW, CPUT and CPUC stop in High-Z.
0
1
11 MULT0
Only for reading the hardware setting of the Pin11 MULT0 value.
Rev 1.0,November 21, 2006
Page 5 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
