CY28339
Pin Definitions
Pin Number
Name
I/O
Description
47
1
REF0
XIN
3.3V 14.318 MHz clock output.
14.318 MHz crystal input.
2
XOUT
14.318 MHz crystal input.
43, 42,
39, 38
CPUT1,CPUC1
CPUT2, CPUC2
Differential CPU clock outputs.
29
31
20
3V66_0
3.3V 66 MHz clock output.
3V66_1/VCH
66IN/3V66_5
3.3V selectable through SMBus to be 66 MHz or 48 MHz.
66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal
VCO.
17, 18, 19
6
66BUFF [2:0] /3V66
[4:2]
66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO.
PCIF
33 MHz clocks divided down from 66Input or divided down from 3V66; PCIF
default is free-running.
8, 9, 10, 12, 13, 14, PCI [0:2]
PCI [4:6]
PCI [7:8]
PCI clock outputs divided down from 66Input or divided down from 3V66;
PCI [7:8] are configurable as free-running PCI through SMBus.[2]
4, 5
35
34
36
46
37
USB_48M
DOT_48M
S2
Fixed 48 MHz clock output.
Fixed 48 MHz clock output.
Special 3.3V three-level input for Mode selection.
3.3V LVTTL inputs for CPU frequency selection.
S1
IREF
A precision resistor is attachedtothis pinwhichis connected to the internal
current reference.
21
30
45
24
PD#
3.3V LVTTL input for Power_Down# (active LOW).
3.3V LVTTL input for PCI_STOP# (active LOW).
3.3V LVTTL input for CPU_STOP# (active LOW).
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1]
inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD#
is sampled LOW, the status of this input will be ignored.
25
26
SDATA
SCLK
SMBus-compatible SDATA.
SMBus-compatible SCLK.
3.3V power supply for outputs.
11, 15, 28, 40, 44, VDD_PCI,
48
VDD_3V66,
VDD_CPU,VDD_REF
33
22
VDD_48 MHz
VDD_CORE
3.3V power supply for 48 MHz.
3.3V power supply for phase-locked loop (PLL).
Ground for outputs.
3, 7, 16, 27, 32, 41 GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
GND_CPU
23
GND_CORE
Ground for PLL.
Note:
2. PCI3 is internally disabled and is not accessible.
Rev 1.0,November 25, 2006
Page 2 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
