CY28330
Table 4. Byte Read and Byte Write protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Start
Bit
1
Start
2:8
9
Slave address - 7 bits
Write = 0
2:8
9
Slave address - 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
Command Code - 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
11:18
Command Code - 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
11:18
19
20:27
28
Acknowledge from slave
Data byte from master - 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address - 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave - 8 bits
Not Acknowledge
Stop
30:37
38
39
Serial Control Registers
Byte 0: Frequency and Spread Spectrum Control Register
Bit
@Pup
Description
7
Inactive = 0 Write Disable (write once). A 1 written to this bit after a 1 has been written to Byte0 bit0 will perma-
nently disable modification of all configuration registers until the part has been powered off. Once
the clock generator has been Write Disabled, the SMBus controller should still accept and
acknowledge subsequent write cycles but it should not modify any of the registers.
6
Inactive = 0 Spread Spectrum enable (0=disable, 1=enable). This bit provides a SW programmable control for
spread spectrum clocking. See Table 5. The readback version of this bit is the hardware strapped
value such that the SW has the ability to know each state, either by readback or by writing the SSE bit.
5
4
3
2
1
0
0
ATPG Mode. 0 = disable, 1 = enable. See Byte 8, bit 7.
FS(3) (corresponds to Frequency Selection. See Table 1.
FS(2) (corresponds to Frequency Selection. See Table 1.
FS(1) (corresponds to Frequency Selection. See Table 1.
FS(0) (corresponds to Frequency Selection. See Table 1.
FS3 pin
FS2 pin
FS1 pin
FS0 pin
Inactive = 0 Write Enable. A 1 written to this bit after power up will enable modification of all configuration registers
and subsequent 0's written to this bit will disable modification of all configuration except this single
bit. Note that block write transactions to the interface will complete, however unless the interface has
been previously un-locked, the writes will have no effect. The effect of writing this bit does not take
effect until the subsequent block write command.
Table 5. Spread Spectrum Enable
Pin 44
B0b6
Spread Enable
0
0
1
1
0
1
0
1
Off
On
On
On
Rev 1.0,November 21, 2006
Page 4 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
