CY28330
Byte 9: Dial-a-Frequency™ Control Register M
Bit
7
@Pup
0
Description
CPU output skew; 0 = normal, 1 = -200ps Pin 41 to Pin 7
6
R5
R4
R3
R2
R1
R0
0
These bits are for programming the PLL’s internal R register. This access allows the user
to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that
are generated from the same PLL, such as PCI, remain at their existing ratios relative to
the CPU clock.
5
4
3
2
1
0
When this bit = 1, it enables the Dial-a-Frequency N and R bits to be multiplexed into the
internal N and R registers. When this bit = 0, the ROM based N and R values are loading
into the internal N and R registers.
ROM
N Register
SMBus
Latch
Byte8
Byte8 Write
R Register
SMBus
Byte9
Byte9 Write
DAFEN
Figure 1. Dial-a-Frequency Register Loading
output may not occur immediately after this time as the PLL
needs to be locked and will not output an invalid frequency.
The CPU frequencies are defined from the hardware-sampled
inputs. Additional frequencies and operating states can be
selected through the SMBus programmable interface.
Dial-a-Frequency Feature
Dial-a-Frequency gives the designer direct access to the
reference divider (M) and the feedback divider (N) of the
internal Phase Lock Loop (PLL). The algorithm is the same for
all P values, which is Fcpu = (P * N) / M with the following
conditions. M = (20..56), N = (21..127) and N > M > N/2. ‘P’ is
a large value constant that translates the output of the PLL into
the CPU frequency. The Value of ‘P’ is relative to the latest
frequency selected in the device prior to enabling the
Dial-a-Frequency feature. Furthermore, P is an indication that
the frequency ratios between the CPU, SDRAM, AGP (3V66),
and PCI clock outputs remains unchanged when the
Dial-a-Frequency feature is enabled.
Spread spectrum modulation is required for all outputs derived
from the internal CPU PLL2 (see Block Diagram). This include
the CPU(0:1), PCI33(0:5), PCI33_F and PCI33_HT66(0:2).
The REF (0:2), USB and 24_48 clocks are not affected by the
spread spectrum modulation. The spread spectrum
modulation is set for both center and down modes using linear
and Lexmark profiles for amounts of 0.5% and 1.0% at a
33KHz rate.
The CPU clock driver is of a push-pull type for the differential
outputs, instead of the AMD Athlon¥ open-drain style. The
CPU clock termination has been derived such that a 15-40
ohm, 3.3V output driver can be used for the CPU clock.
Table 10.
FS(3:0)
P
XXXX
95995000
The PCISTOP# signal provides for synchronous control over
the any output, except the PCI33_F, that is running at 33MHz.
If the PCI33_HT66 outputs are configured to run at 66MHz will
not be stopped by this signal. The PCISTOP# signal is
sampled by an internal PCI clock such that once it is sensed
low or active, the 33MHz signals are stopped on the next high
to low transition such that there is always a valid high signal.
Operation
Pin strapping on any configuration pin is based on a 10K ohm
resistor connected to either 3.3V (VDD) or ground (VSS).
When the VDD supply goes above 2.0V, the Power-On-Reset
circuitry latches all of the configuration bits into their respective
registers and then allows the outputs to be enabled. The
Rev 1.0,November 21, 2006
Page 8 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
