CY28330
Clock Generator for AMD™ Hammer
Features
• Supports AMD
Hammer CPU
• 2 differential Pair of CPU Clocks
• 6 Low Skew/Jitter PCI Clocks
• 1 Free-running PCI Clock
• 3 Low Skew/Jitter AGP/HT Clocks
• 148M Output for USB
• 1 programmable 24M or 48M for FDC
• 3 REF 14.318MHz Clocks
• Dial-a-Frequency
Programmability
• Cypress Spread Spectrum for Best EMI Reduction
• SMBus Register Programmable Options
• 5V Tolerance SCLK and SDATA Lines
• 3.3V Operation
• Power Management Control Pins
• 48 Pin SSOP Package
Table 1. Frequency Table (MHz)
[1]
FS
(3:0)
CPU
PCI_HT
SEL
PCI_HT
PCI
VC0
CPU PCI_H PCI
Div T Div Div
0000 Hi-Z
0001 XIN
0001 XIN
0010 100.0
0011 100.0
0100 100.0
0101 133.3
0110 166.7
0111 200.0
1000 105.0
1001 110.0
1010 115.0
1011 120.0
1100 140.0
1101 150.0
1110 160.0
1111 180.0
=
X
0
1
Hi-Z
XIN/3
XIN/6
Hi-Z
XIN/6
XIN/6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3/6
3/6
3/6
4/8
5/10
6/12
3/6
3/6
3/6
4/8
4/8
5/10
5/10
6/12
6
6
6
8
10
12
6
6
6
8
8
10
10
12
0/1 66.7/33.3 33.31 200
0/1 66.7/33.3 33.31 200
0/1 66.7/33.3 33.31 200
0/1 66.7/33.3 33.31 266.6
0/1 66.7/33.3 33.31 333.3
0/1 66.7/33.3 33.31 400.0
0/1 70.0/35.0 35.00 210.0
0/1 73.3/36.7 36.67 220.0
0/1 76.7/38.3 38.33 230.0
0/1 60.0/30.0 30.00 240.0
0/1 70.0/35.0 35.00 280.0
0/1 60.0/30.0 30.00 300.0
0/1 64.0/32.0 32.00 320.0
0/1 60.0/30.0 30.00 360.0
Block Diagram
X
IN
XU
OT
14.31818M z
H
X L
TA
/4
P
LL1
24_48M
H
RF
E (0:2)
Pin Configuration
FS0/REF0
VDD
XIN
XOUT
VSS
*PCI33HT66SEL#
PCI33_HT66_0
PCI33_HT66_1
VDD
VSS
PCI33_HT66_2
*SRESET#/PD#
PCI33_0
PCI33_1
VSS
VDD
PCI33_2
PCI33_3
VDD
VSS
PCI33_4
PCI33_5
FS3/PCI33_F
PCISTOP#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Pull-up
UB
S
/2
24_48M /
H
24_48S L#
E
FS
(0:3)
P IS P
C TO #
SRA
PED
C
ontrol Logic
SEE D
R S T#/P #
S LK
C
SA
D TA
P
LL2
CU
P T(0:1)
C U (0:1)
PC
/N
P I33_F
C
S P
TO
P I33_(0:5)
C
C TL
N
P I33_H
C
T66_(0:2)
FS1/REF1
VSS
VDD
FS2/REF2
*SPREAD
VDDA
VSSA
CPUT0
CPUC0
VSS
VDD
CPUT1
CPUC1
VDD
VSS
VSSF
VDDF
USB
VSS
VDD
24_48MHz/SEL#
VSS
SDATA
SCLK
*
= 150 K
Note:
1. All outputs except XOUT will be three-stated when FS(3:0) = 0000.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 14
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