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CY28329ZCT 参数 Datasheet PDF下载

CY28329ZCT图片预览
型号: CY28329ZCT
PDF下载: 下载PDF文件 查看货源
内容描述: 133 MHz的扩频时钟合成器/驱动器,具有差分输出的CPU [133 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs]
分类和应用: 晶体驱动器外围集成电路光电二极管时钟
文件页数/大小: 16 页 / 241 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28329  
Switching Characteristics Over the Operating Range[8]  
Parameter  
t1  
t2  
Output  
Description  
Output Duty Cycle[9]  
Rise Time  
Test Conditions  
Measured at 1.5V  
Min.  
45  
Max.  
55  
Unit  
%
All  
CPU  
Measured differential waveform from  
–0.35V to +0.35V  
175  
700  
ns  
t2  
USB, REF,  
DOT  
Rising Edge Rate  
Between 0.4V and 2.4V  
0.5  
2.0  
ns  
t2  
t3  
PCI, 3V66  
CPU  
Rising Edge Rate  
Fall Time  
Between 0.4V and 2.4V  
1.0  
4.0  
V/ns  
ps  
Measured differential waveform from  
–0.35V to +0.35V  
175  
700  
t3  
USB, REF,  
DOT  
Falling Edge Rate  
Between 2.4V and 0.4V  
0.5  
1.0  
2.0  
ns  
t3  
t4  
t5  
t5  
t6  
t7  
t8  
PCI, 3V66  
CPU  
Falling Edge Rate  
CPU-CPU Skew  
Between 2.4V and 0.4V  
Measured at Crossover  
Measured at 1.5V  
4.0  
150  
500  
175  
500  
3.5  
V/ns  
ps  
3V66 [0:1]  
66BUFF[0:2]  
PCI  
3V66-3V66 Skew  
ps  
66BUFF-66BUFF Skew  
PCI-PCI Skew  
Measured at 1.5V  
ps  
Measured at 1.5V  
ps  
3V66, PCI  
CPU  
3V66-PCI Clock Skew  
Cycle-Cycle Clock Jitter  
3V66 leads. Measured at 1.5V  
1.5  
ns  
Measured at Crossover t8 = t8A – t8B  
With all outputs running  
150  
ps  
t9  
3V66  
USB, DOT  
PCI  
Cycle-Cycle Clock Jitter  
Cycle-Cycle Clock Jitter  
Cycle-Cycle Clock Jitter  
Cycle-Cycle Clock Jitter  
POR timing  
Measured at 1.5V t9 = t9A – t9B  
Measured at 1.5V t9 = t9A – t9B  
Measured at 1.5V t9 = t9A – t9B  
Measured at 1.5V t9 = t9A – t9B  
Measured at 1.5V[10, 11]  
250  
350  
500  
1000  
4.0  
ps  
ps  
ps  
ps  
ms  
mV  
V
t9  
t9  
t9  
REF  
t10  
ALL  
1.0  
CPU  
Rise/Fall Matching  
Measured with test loads[12, 13]  
Measured with test loads[13]  
235  
1.45  
Voh  
Vol  
CPU  
High-level Output Voltage  
including overshoot  
0.92  
–0.2  
CPU  
CPU  
Low-level Output Voltage  
including undershoot  
Measured with test loads[13]  
Measured with test loads[13]  
0.35  
V
V
Vcrossover  
Crossover Voltage  
0.250 0.550  
Notes:  
8. All parameters specified with loaded outputs.  
9. Duty cycle is measured at 1.5V when V = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V.  
10. POR starts when V reaches 1.5V.  
DD  
DD  
DD  
11. All PULL-UPs must ramp at the same rate as V  
.
DD  
12. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trn is an intersecting falling edge.  
13. The test load is R = 33.2:, R = 49.9: in test circuit.  
s
p
Rev 1.0,November 24, 2006  
Page 8 of 16