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CY28329ZCT 参数 Datasheet PDF下载

CY28329ZCT图片预览
型号: CY28329ZCT
PDF下载: 下载PDF文件 查看货源
内容描述: 133 MHz的扩频时钟合成器/驱动器,具有差分输出的CPU [133 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs]
分类和应用: 晶体驱动器外围集成电路光电二极管时钟
文件页数/大小: 16 页 / 241 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28329  
Data Byte 4:  
Power On  
Default  
Bit  
Bit 7  
Pin#  
Name  
Pin Description  
Type  
Reserved, set = 0  
Reserved, set = 0  
R
R
0
0
1
Bit 6  
Bit 5  
33  
3V66_0  
3V66_0 Output Enable  
1 = Enabled; 0 = Disabled  
R/W  
Bit 4  
Bit 3  
35  
24  
3V66_1/VCH  
66IN/3V66_5  
3V66_1/VCH Output Enable  
1 = Enabled; 0 = Disabled  
R/W  
R/W  
1
1
3V66_5 Output Enable  
1 = Enable; 0 = Disable  
Note: This bit should be used when pin 24 is configured as  
3V66_5 output. do not clear this bit when pin 24 is  
configured as 66IN input.  
Bit 2  
Bit 1  
Bit 0  
23  
22  
21  
66BUFF2  
66BUFF1  
66BUFF0  
66-MHz Buffered 2 Output Enable  
1 = Enabled; 0 = Disabled  
R/W  
R/W  
R/W  
1
1
1
66-MHz Buffered 1 Output Enable  
1 = Enabled; 0 = Disabled  
66-MHz Buffered 0 Output Enable  
1 = Enabled; 0 = Disabled  
Data Byte 5:  
Power On  
Default  
Bit  
Bit 7  
Pin#  
Name  
Pin Description  
Reserved, set = 0  
Type  
R
0
0
0
0
0
0
0
0
Bit 6  
Reserved, set = 0  
R
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
21,22,23  
38  
66BUFF [2:0]  
DOT  
Tpd 66IN to 66BUFF propagation delay control  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
DOT edge rate control  
USB edge rate control  
39  
USB  
Byte 6: Vendor ID  
Power On  
Default  
Bit  
Description  
Type  
R
Bit 7  
Revision Code Bit 3  
Revision Code Bit 2  
Revision Code Bit 1  
Revision Code Bit 0  
Vendor ID Bit 3  
0
0
0
0
1
0
0
0
Bit 6  
R
Bit 5  
R
Bit 4  
R
Bit 3  
R
Bit 2  
Vendor ID Bit 2  
R
Bit 1  
Vendor ID Bit 1  
R
Bit 0  
Vendor ID Bit 0  
R
Rev 1.0,November 24, 2006  
Page 6 of 16