CY28329
Data Byte 1:
Power On
Default
Bit
Bit 7
Pin#
–
Name
Description
Type
CPU Mult0 Value
R
HW
Bit 6
53, 54
CPU3
CPU3#
CPU3 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 5
Bit 4
Bit 3
Bit 2
–
–
–
–
Reserved, set = 0
R/W
R/W
R/W
R/W
0
0
0
1
–
–
Reserved, set = 0
Reserved, set = 0
44, 45
CPU2
CPU2#
CPU2 Output Enable
1 = Enabled; 0 = Disabled
Bit 1
Bit 0
48, 49
51, 52
CPU1
CPU1#
CPU1Output Enable
1 = Enabled; 0= Disabled
R/W
R/W
1
1
CPU0
CPU0#
CPU0 Output Enable
1 = Enabled; 0 = Disabled
Data Byte 2:
Power On
Default
Bit
Bit 7
Pin#
–
Name
–
Pin Description
Type
R
Reserved, set = 0
0
1
Bit 6
18
PCI6
PCI6 Output Enable
1 = Enabled; 0 = Disabled
R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
17
16
13
12
11
10
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCI5 Output Enable
1 = Enabled; 0 = Disabled
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
PCI4 Output Enable
1 = Enabled; 0 = Disabled
PCI3 Output Enable
1 = Enabled; 0 = Disabled
PCI2 Output Enable
1 = Enabled; 0 = Disabled
PCI1 Output Enable
1 = Enabled; 0 = Disabled
PCI0 Output Enable
1 = Enabled; 0 = Disabled
Data Byte 3:
Power On
Default
Bit
Bit 7
Pin#
38
39
7
Name
DOT
Pin Description
Type
R/W
R/W
R/W
DOT 48 MHz Output Enable, 1 = enabled, 0 = disabled
USB 48 MHz Output Enable, 1 = enabled, 0 = disabled
1
1
0
Bit 6
USB
Bit 5
PCI_F2
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Bit 4
Bit 3
6
5
PCI_F1
PCI_F0
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
R/W
0
0
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
Bit 2
Bit 1
Bit 0
7
6
5
PCI_F2
PCI_F1
PCI_F0
PCI_F2 Output Enable, 1 = enabled, 0 = disabled
PCI_F1Output Enable, 1 = enabled, 0 = disabled
PCI_F0 Output Enable, 1 = enabled, 0 = disabled
R/W
R/W
R/W
1
1
1
Rev 1.0,November 24, 2006
Page 5 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
