CY28316
Byte 3: Control Register 3
Bit
Pin#
Name
SDRAM8:11
SEL_48MHz
Default
Description
Bit 7
Bit 6
21, 20, 18, 17
–
1
0
(Active/Inactive).
0 = 24 MHz.
1 = 48 MHz.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
26
48MHz
1
1
1
1
1
1
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
(Active/Inactive).
25
24_48MHz
SDRAM6:7
SDRAM4:5
SDRAM2:3
SDRAM0:1
29, 28
32, 31
35, 34
38, 37
Byte 4: Control Register 4
Bit
Bit 7
Pin#
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
Description
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 5: Control Register 5
Bit
Bit 7
Pin#
–
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
REF1
Default
Description
0
0
0
0
0
0
1
1
Reserved.
Bit 6
–
Reserved.
Bit 5
–
Reserved.
Bit 4
–
Reserved.
Bit 3
–
Reserved.
Bit 2
–
Reserved.
Bit 1
46
47
(Active/Inactive).
(Active/Inactive).
Bit 0
REF0
Byte 6: Watchdog Timer Register
Bit
Name
PCI_Skew1
PCI_Skew0
Default
Pin Description
Bit 7
Bit 6
0
0
PCI skew control.
00 = Normal.
01 = –500 ps.
10 = Reserved.
11 = +500 ps.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
1
1
1
1
1
0
These bits store the time-out value of the Watchdog Timer. The scale of the
timer is determined by the prescaler. The timer can support a value of 150 ms
to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec,
itcan support avaluefrom 2.5 sec to 80sec. When theWatchdogTimer reaches
“0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is
enabled.
WD_PRE_
SCALER
0 = 150 ms.
1 = 2.5 sec.
Rev 1.0,November 20, 2006
Page 6 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
