CY28316
Byte 9: System RESET and Watchdog Timer Register (continued)
Bit
Name
Default
Pin Description
CPU0:1 clock output drive strength.
0 = Normal.
Bit 0
CPU0:1_DRV
0
1 = High Drive.
Byte 10: Skew Control Register
Bit
Name
CPU0:1_Skew2
CPU0:1_Skew1
CPU0:1_Skew0
Default
Description
Bit 7
Bit 6
Bit 5
0
0
0
CPU0:1 output skew control.
000 = Normal.
001 = –150 ps.
010 = –300 ps.
011 = –450 ps.
100 = +150 ps.
101 = +300 ps.
110 = +450 ps.
111 = +600 ps.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Byte 11: Recovery Frequency N-Value Register
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, CY28316 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency when a Watchdog Timer time-out occurs. The setting
of FS_Override bit determines the frequency ratio for CPU and PCI. When it
is cleared, CY28316 will use the same frequency ratio stated in the Latched
FS[4:0] register. When it is set, CY28316 will use the frequency ratio stated in
the SEL[4:0] register. CY28316 supports programmable CPU frequencies
ranging from 50 MHz to 248 MHz. CY28316 will change the output frequency
whenever there is an update to either ROCV_FREQ_N[7:0] or
ROCV_FREQ_M[6:0]. Therefore it is recommended to use word or block Write
to update both registers within the same SMBus bus operation.
Byte 12: Recovery Frequency M-Value Register
Bit
Name
Default
Pin Description
Bit 7
ROCV_FREQ_SEL
0
ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog Timer time-out occurs. The clock generator will automatically switch
to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0].
1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0].
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_M6
ROCV_FREQ_M5
ROCV_FREQ_M4
ROCV_FREQ_M3
ROCV_FREQ_M2
ROCV_FREQ_M1
ROCV_FREQ_M0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, CY28316 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency when a Watchdog Timer time-out occurs. The setting
of the FS_Override bit determines the frequency ratio for CPU, SDRAM, and
PCI. When it is cleared, CY28316 will use the same frequency ratio stated in
the Latched FS[4:0] register. When it is set, CY28316 will use the frequency
ratio stated in the SEL[4:0] register. CY28316 supports programmable CPU
frequencies ranging from 50 MHz to 248 MHz. CY28316 will change the output
frequency whenever there is an update to either ROCV_FREQ_N[7:0] or
ROCV_FREQ_M[6:0]. Therefore, itis recommendedtousewordor block Write
to update both registers within the same SMBus bus operation.
Rev 1.0,November 20, 2006
Page 8 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
