CY2277A
Pin Summary
Name
VDDQ3
VDDQ2
VDDCPU
AVDD
Pins
Description
7, 15, 21, 28, 34
3.3V Digital voltage supply
IOAPIC Digital voltage supply, 2.5V
CPU Digital voltage supply, 2.5V or 3.3V
3.3V Analog voltage supply
46
40
25, 48
VSS
3, 10, 17, 24, 31, 37, 43 Ground
XTALIN[1]
XTALOUT[1]
MODE
SEL
4
Reference crystal input
5
Reference crystal feedback
6
Mode select input, enables power management features
18
Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)
SDATA
19
20
44
47
SMBus serial data input for serial configuration port
SCLK
SMBus serial clock input for serial configuration port
PWR_DWN
PWR_SEL
Active low control input to put osc., PLLs, and outputs in power down state
Power select input, indicates whether VDDCPU is at 2.5V or 3.3V
HIGH = 3.3V, LOW=2.5V (internal pull-up to VDD
)
SDRAM7/PCI_STOP 26
SDRAM6/CPU_STOP 27
SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW
SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW
SDRAM[0:5]
CPUCLK[0:3]
PCICLK[0:5]
PCICLK_F
IOAPIC
36, 35, 33, 32, 30, 29
SDRAM clock outputs, have same frequency as CPU clocks
CPU clock outputs
42, 41, 39, 38
9, 11, 12, 13, 14, 16
PCI clock outputs
8
PCI clock output, free-running
45
IOAPIC clock output
REF[0:1]
1, 2
22, 23
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
USB or IO clock outputs, frequency selected by serial word
USBCLK/IOCLK
Note:
1. For best accuracy, use a parallel-resonant crystal, C
= 18 pF.
LOAD
Table 1. CY2277A Selector Guide
Clock Outputs
-1/-1M
-3
-7M
4
-12/-12M/-12I
CPU (60, 66.6 MHz)
CPU (33.3, 66.6 MHz)
CPU (SMBus selectable)
PCI (CPU/2)
4
--
4
--
--
4
--
--
--
--
--
7[2]
6/8
2
7[2]
6/8
2
7[2]
6/8
2
7[2]
6/8
2
SDRAM
USB/IO (48 or 24 MHz)
IOAPIC (14.318 MHz)
Ref (14.318 MHz)
1
1
1
1
2
2
2
2
CPU-PCI delay
1–6 ns
1–6 ns
<1 ns
1–4 ns
Note:
2. One free-running PCI clock
Rev 1.0,November 25, 2006
Page 2 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
