Preliminary
STK14EC16
SRAM WRITE CYCLES #1, #2, and #3
SYMBOLS
STK14EC16-15
STK14EC16-25
STK14EC16-45
NO.
PARAMETER
UNITS
#1
#2
#3
Alt.
MIN
15
10
15
15
5
MAX
MIN
25
20
20
20
10
0
MAX
MIN
45
30
30
30
15
0
MAX
15
16
17
18
19
20
21
22
23
24
25
t
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
AVAV
t
t
t
t
Write Pulse Width
WLWH
WLEH
WLBH
WP
CW
t
t
t
t
t
t
Chip Enable to End of Write
Byte Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
BLWH
DVWH
WHDX
ELEH
BLEH
DVEH
EHDX
ELBH
BLBH
DVBH
BHDX
t
t
t
t
t
t
t
t
t
DW
t
0
DH
t
t
t
AVBH
10
0
20
0
30
0
AVWH
AVEH
AW
t
t
t
t
AS
AVWL
AVEL
AVBL
t
t
t
t
0
0
0
WHAX
e, g
EHAX
BHAX
WR
t
t
7
10
15
WLQZ
WZ
t
t
3
3
3
WHQX
OW
Note g: If W is low when E goes low, the outputs remain in the high-impedance state.
Note h: E or W must be ≥ VIH during address transitions.
g,h
SRAM WRITE CYCLE #1: W Controlled
tAVAV (15)
Address
Address Valid
tELWH (17)
tWHAX (23)
E
tBLWH (18)
LB, UB
W
tAVWH (21)
tWLWH (16)
tAVWL
(22)
tWHDX (20)
tDVWH (19)
Input Data Valid
Data Input
tWLQZ (24)
tWHQX (25)
High Impedance
Data Output
Previous Data
g,h
SRAM WRITE CYCLE #2: E Controlled
tAVAV (15)
Address Valid
Address
E
tAVWL (22)
tEHAX (23)
tELEH (17)
tBLEH (18)
tWLEH (16)
LB , UB
W
tDVEH (19)
Input Data Valid
High Impedance
tEHDX (20)
Data Input
Data Output
7
Rev 1.1
Document Control #ML0061
Jan, 2008
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
