Preliminary
STK14EC16
1
2
3
4
5
6
NC
1
A17
A16
A15
54
53
52
51
50
49
48
47
46
45
HSB
NC
A17
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A0
2
A1
A2
2
3
LB
G
A0
A3
A1
A4
A2 NC
DQ0
A
B
C
D
E
F
3
A1
4
A16
A3
A4
A2
A3
A15
5
G
4
DQ8 UB
E
6
G
UB
5
A4
E
7
UB
DQ9 DQ10 A5
VSS DQ11 A17
A6 DQ1 DQ2
A7 DQ3 VCC
6
LB
E
DQ0
LB
8
DQ15
DQ14
DQ13
DQ12
7
DQ0
DQ15
DQ14
9
DQ1
DQ2
DQ3
DQ1
DQ2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8
DQ13
DQ12
VSS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
9
VCC DQ12
DQ14 DQ13
VCAP A16 DQ4 VSS
A14 A15 DQ5 DQ6
DQ3
VCC
VSS
(TOP)
(TOP)
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
VSS
VSS
VCC
DQ4
DQ5
DQ6
DQ7
VCC
DQ11
DQ4
G
DQ15 HSB A12 A13
NC A8
A9 A10
(TOP)
W
DQ7
NC
DQ11
DQ10
DQ9
DQ5
DQ6
DQ7
DQ10
DQ9
DQ8
DQ8
H
A11
W
A5
VCAP
A14
A6
A7
A8
A13
VCAP
A14
A13
A12
A11
W
A5
48-Ball FBGA
A12
A11
A10
NC
NC
NC
A6
A7
A8
A9
NC
NC
NC
A9
A10
44-Pin TSOP-II
54-Pin TSOP-II
(See full mechanical drawings on pages 18 – 20)
PIN DESCRIPTIONS
Pin Name
-A
I/O
Description
Address: The 18 address inputs select one of 262,144 words in the nvSRAM array
Data: Bi-directional 16-bit data bus for accessing the nvSRAM
A
Input
I/O
17
0
DQ -DQ
15
0
E
Input
Input
Input
Input
Input
Chip Enable: The active low E input selects the device
LB
UB
W
G
Byte Write Select Input: Controls DQ7-DQ0 (unselected byte will not write or read).
Byte Write Select Input: Controls DQ15-DQ8 (unselected byte will not write or read).
Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high causes the DQ pins
to tri-state.
V
Power Supply
I/O
Power: 3.0V +20%, -10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress (also low during power up while busy). When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected.
(Connection Optional).
V
V
Power Supply
Autostore Capacitor: Supplies power to the nvSRAM during a power loss to store data from SRAM to nonvolatile storage ele-
ments.
CAP
Power Supply
No Connect
Ground
SS
NC
This pin is not connected to the die. (Do not connect in design; reserved for future use)
3
Rev 1.1
Document Control #ML0061
Jan, 2008
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
