Preliminary
STK14EC16
g,h
SRAM WRITE CYCLE #3: LB, UB Controlled
t AVAV (15)
Address Valid
Address
t ELBH (17)
E
t
(23)
t
(18)
(16)
t
(22)
BHAX
AVBL
BLBH
LB,UB
W
tAVBH (21)
tWLBH
t
BHDX (20)
t
DVBH(19)
Input Data Valid
Data Input
High Impedance
Data Output
AutoStore™/POWER-UP RECALL
SYMBOLS
NO.
STK14EC16
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
20
26
27
28
29
t
t
Power-up RECALL Duration
ms
ms
V
i
j
HRECALL
STORE
t
STORE Cycle Duration
12.5
2.65
HLHZ
V
Low Voltage Trigger Level
SWITCH
CCRISE
V
V
Rise Time
150
μs
CC
Note i: tHRECALL starts from the time VCC rises above VSWITCH
Note j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
AutoStore™/POWER-UP RECALL
VCC
VSWITCH
(28)
tVCCRISE (29)
tSTORE (27)
tSTORE (27)
**
**
AutoStore
POWER-UP
RECALL
tHRECALL (26)
tHRECALL (26)
Read & Write
Inhibited
POWER DOWN
AutoStore
POWER-UP
RECALL
POWER-UP
RECALL
BROWN OUT
AutoStore
Read & Write
Read & Write
** AutoStore occures only if at least one SRAM Write has happened
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH
Rev 1.1
Document Control #ML0061
Jan, 2008
8
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
