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24C04AT-E/SL 参数 Datasheet PDF下载

24C04AT-E/SL图片预览
型号: 24C04AT-E/SL
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 512X8, Serial, CMOS, PDSO14, 0.150 INCH, PLASTIC, SOIC-14]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 15 页 / 809 K
品牌: ROCHESTER [ Rochester Electronics ]
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24C04A  
4.0  
SLAVE ADDRESS  
5.0  
BYTE PROGRAM MODE  
The chip address inputs A1 and A2 must be externally  
connected to either VCC or ground (VSS), thereby  
assigning a unique address to each device. A0 is not  
used on the 24C04A and must be connected to either  
VCC or VSS. Up to four 24C04A devices may be con-  
nected to the bus. Chip selection is then accomplished  
through software by setting the bits A1 and A2 of the  
slave address to the corresponding hard-wired logic lev-  
els of the selected 24C04A. After generating a START  
condition, the bus master transmits the slave address  
consisting of a 4-bit device code (1010), followed by the  
chip address bits A0, A1 and A2. The seventh bit of that  
byte (A0) is used to select the upper block (addresses  
100—1FF) or the lower block (addresses 000—0FF) of  
the array.  
In this mode, the master sends addresses and one  
data byte to the 24C04A.  
Following the START signal from the master, the device  
code (4-bits), the slave address (3-bits), and the R/W  
bit, which is logic LOW, are placed onto the bus by the  
master. This indicates to the addressed 24C04A that a  
byte with a word address will follow after it has gener-  
ated an acknowledge bit. Therefore the next byte trans-  
mitted by the master is the word address and will be  
written into the address pointer of the 24C04A. After  
receiving the acknowledge, the master device trans-  
mits the data word to be written into the addressed  
memory location. The 24C04A acknowledges again  
and the master generates a STOP condition. This ini-  
tiates the internal programming cycle (Figure 6-1).  
The eighth bit of the slave address determines if the  
master device wants to read or write to the 24C04A  
(Figure 4-1).  
The 24C04A monitors the bus for its corresponding  
slave address all the time. It generates an acknowl-  
edge bit if the slave address was true and it is not in a  
programming mode.  
FIGURE 4-1: SLAVE ADDRESS  
ALLOCATION  
START  
READ/WRITE  
SLAVE ADDRESS  
R/W  
A
1
0
1
0
A2  
A1  
A0  
2004 Microchip Technology Inc.  
DS11183F-page 5