24C04A
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Symbol
Min.
Typ
Max.
Units
Remarks
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
—
—
—
—
—
—
100
—
kHz
ns
Clock high time
Clock low time
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
ns
TF
—
ns
THD:STA
4000
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
—
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
Data output delay time
STOP condition setup time
Bus free time
THD:DAT
TSU:DAT
TAA
0
—
—
—
—
—
—
—
ns
ns
250
300
4700
4700
3500
—
(Note 1)
TSU:STO
TBUF
ns
ns
—
Time the bus must be free
before a new transmission
can start
Input filter time constant
(SDA and SCL pins)
TI
—
—
—
100
ns
Program cycle time
TWC
.4
.4N
—
1
N
ms
ms
Byte mode
Page mode, N=# of bytes
Endurance
—
1M
—
cycles
25°C, Vcc = 5.0V, Block
Mode (Note 2)
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
THD:STA
SDA
OUT
2004 Microchip Technology Inc.
DS11183F-page 3
ROCHESTER [ Rochester Electronics ]
