FS714x Programmable Phase-Locked Loop Clock Generator
Data Sheet
When not using the crystal oscillator, it is preferred to connect XIN to VSS. Do not connect to XOUT.
When not using the REF input, it is preferred to leave it floating or connected to VDD
.
4.1.6. Feedback Divider Source MUX
The source of frequency for the feedback divider may be selected to be either the output of the post divider or the output of the VCO by
the FBKDSRC bit.
Ordinarily, for frequency synthesis, the output of the VCO is used. Use the output of the post divider only where a deterministic phase
relationship between the output clock and reference clock are desired (line-locked mode, for example).
4.1.7. Device Shutdown
Two bits are provided to effect shutdown of the device if desired, when it is not active. SHUT1 disables most externally observable
device functions. SHUT2 reduces device quiescent current to absolute minimum values. Normally, both bits should be set or cleared
together.
Serial communications capability is not disabled by either SHUT1 or SHUT2.
4.2 Differential Output Stage
The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the
programming registers.
If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink
current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of output
sink current to IPRG current is 13:1. Source current for the CLKx pins is provided by the pull-up resistors that are part of the Thévenin
termination.
4.2.1. Example
Assume that it is desired to connect a PECL-type fanout buffer right next to the FS7140.
Further assume:
• VDD = 3.3V
• Desired VHI = 2.4V
• Desired VLO = 1.6V
• Equivalent RLOAD = 75 ohms
AMI Semiconductor – Dec, 2007 – Rev. 4.0
5
www.amis.com
Specifications subject to change without notice
ROCHESTER [ Rochester Electronics ]
