FS714x Programmable Phase-Locked Loop Clock Generator
Data Sheet
Table 2: FS7145 Pin Descriptions
Pin
1
2
3
4
Type
DI
DIO
DID
P
Name
SCL
SDA
ADDR0
VSS
Description
Serial interface clock (requires an external pull-up)
Serial interface data input/output (requires an external pull-up)
Address select bit “0”
Ground
5
6
7
8
AI
XIN
Crystal oscillator feedback
Crystal oscillator drive
Address select bit “1”
Power supply (+3.3V nominal)
PECL current drive programming
No connection
Ground
Reference frequency input
Synchronization input
Power supply (+3.3V nominal)
Clock output
Inverted clock output
AO
DID
P
AI
-
XOUT
ADDR1
VDD
IPRG
n/c
VSS
REF
SYNC
VDD
CLKP
CLKN
9
10
11
12
13
14
15
16
P
DIU
DIU
P
DO
DO
Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-up; DID = Input with Internal Pull-down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin
4.0 Functional Block Diagram
4.1 Phase Locked Loop (PLL)
The PLL is a standard phase- and frequency-locked loop architecture. The PLL consists of a reference divider, a phase-frequency
detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider.
The reference frequency (generated by either the on-board crystal oscillator or an external frequency source), is first reduced by the
reference divider. The integer value that the frequency is divided by is called the modulus and is denoted as NR for the reference
divider. This divided reference is then fed into the PFD.
The VCO frequency is fed back to the PFD through the feedback divider (the modulus is denoted by NF).
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at
the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is then:
This basic PLL equation can be rewritten as
A post divider (actually a series combination of three post dividers) follows the PLL and the final equation for device output frequency is:
AMI Semiconductor – Dec, 2007 – Rev. 4.0
3
www.amis.com
Specifications subject to change without notice
ROCHESTER [ Rochester Electronics ]
