RT3663BH
Functional Block Diagram
UVLO
MUX
ADC
GND
SVI2 Interface
Configuration Registers
Control Logic
OFS/OFSA
IBIAS
Loop Control
Protection Logic
Load Line
/Load Line A
From Control Logic
RSET/RSETA
OCP Threshold
TONSETA
PWMA2
RGND
DAC
ERROR
VSETA
Soft-Start & Slew
Rate Control
AMP
+
-
TON
GENA
+
Offset
Cancellation
BOOTA1
PWMA1
+
QRA
-
PWM
CMPA
UGATEA1
PHASEA1
LGATEA1
1-PH
Driver
TONA
FBA
COMPA
Current mirror
IBA1
0.4 x A
i_VDDNB
ISENA1P
ISENA1N
+
+
x2
-
Current
Balance
V064
-
RSETA
IMONAI
Current mirror
IBA2
ISENA2P
ISENA2N
+
Average
IBA1
IBA2
x2
-
Driver
POR
PVCC
IMONA
+
-
OCA
To Protection Logic
OV/UV/NV
OCP_TDCA,
OCP_SPIKEA
From Control Logic
TONSET
VSENA
RGND
DAC
BOOTx
UGATEx
PHASEx
LGATEx
PWM3
ERROR
AMP
PWM1
PWM2
Soft-Start & Slew Rate
Control
VSET
Offset
Cancellation
2-PH
Driver
+
-
+
TON
GEN
FB
-
+
PWM
QR
COMP
CMP
Current mirror
IB1
TON
0.4 x A
i_VDD
ISEN1P
ISEN1N
+
x1
+
-
-
RSET
Current mirror
IB2
V064
ISEN2P
ISEN2N
+
x1
-
Current Balance
IB2
Average
IMONI
Current mirror
IB3
IB1
IB3
ISEN3P
ISEN3N
+
x1
-
SET3
+
-
OC
To Protection Logic
OV/UV/NV
OCP_TDC,
OCP_SPIKE
VSEN
IMON V064/SET3
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3663BH-01 July 2019
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5
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