RT3663BH
Functional Pin Description
Pin No.
Pin Name
Pin Function
3
PWM3
PWM outputs for Channel 3 VDD controller.
VDD controller on-time setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
4
TONSET
5, 8, 9
ISEN1P to ISEN3P Positive current sense input of Channel 1, 2 and 3 for VDD controller.
ISEN1N to ISEN3N Negative current sense input of Channel 1, 2 and 3 for VDD controller.
6, 7, 10
VDD controller voltage sense input. This pin is connected to the terminal of
VDD controller output voltage.
11
VSEN
Output voltage feedback input of VDD controller. This pin is the negative
input of the error amplifier for the VDD controller.
12
13
FB
COMP
RGND
Compensation node of the VDD controller.
Return ground of VDD and VDDNB controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
14
15
Current monitor output for the VDD controller. This pin outputs a voltage
proportional to the output current.
IMON
This pin provides two functions: fixed 0.64v reference voltage output and
current gain ratio setting for VDD and VDDNB controller. Connect a
resistive voltage divider from VCC to GND and connect the joint of the
voltage divider to this pin for current gain ratio setting. The pin also used to
offset the output voltage of the IMON pin and the IMONA pin. Bypass this
pin to GND with a 22nF ceramic capacitor for noise decoupling and pin
setting accuracy.
16
V064/SET3
Current monitor output for the VDDNB controller. This pin outputs a voltage
proportional to the output current.
17
18
IMONA
VDDIO
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System power good input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
19
PWROK
20
21
22
23
24
SVC
SVD
SVT
Serial VID clock input from processor.
Serial VID data input from processor. This pin is a serial data line.
Serial VID telemetry input from VR. This pin is a push-pull output.
Over clocking offset setting for the VDD controller.
OFS
OFSA
Over clocking offset setting for the VDDNB controller.
st
1
platform setting. Platform can use this pin to set OCP_TDC threshold,
25
26
27
SET1
DVID compensation bit1 and internal ramp slew rate.
nd
2
platform setting. Platform can use this pin to set quick response
SET2
threshold, OCP_TDC trigger delay time, DVID compensation bit0 and over
clocking offset enable setting.
Over-current indicator for dual OCP mechanism. This pin is an open-drain
output.
OCP_L
Copyright 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3663BH-01 July 2019
www.richtek.com
3
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