168-pin Low Profile Registered SDRAM DIMMs
256MB, 512MB, 1GB
Preliminary Data Sheet
Pin Descriptions
Symbol
Type
Function
Clocks: All SDRAM input signals are sampled on the positive edge of CK. CK0 is distributed through an on-
board PLL to all devices. CK(1:3) are terminated.
CK(0:3)
Input
Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the
Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until
the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.
CKE(0:1)
Input
Input
Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is
disabled, new commands are ignored but previous operations continue.
S(0:3)#
RAS#, CAS#,
WE#
Input
Input
Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.
BA(0:1)
Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.
Address Inputs: A0-A12 define the row address during the Bank Activate command. A0-A8 define the column
address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual
Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.
The address inputs are also used to program the Mode Register.
A(0:12)
Input
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up
and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after
the CAS latency is satisfied.
Input/
Output
DQ(0:63)
Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable
(2-cycle latency) for read data.
DQMB(0-7)
CB(0:7)
Input
Input/
Output
ECC Check Bits
VDD
VSS
Supply
Supply
Power Supply: +3.3 V
Ground
Input/
Output
Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into
and data out of the presence-detect portion of the module.
SDA
Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to
and from the module
SCL
Input
Input
Input
SA(0-2)
WP
Presence-Detect Address Inputs: These pins are used to configure the presence detect device.
Serial Presence Detect Write Protect: Active high inhibits writes to the SPD EEPROM. WP must be driven low
for normal read/write operations.
REGE
RFU
DNU
NC
Input
Register Enable
-
-
-
Reserved for Future Use: These pins should be left unconnected.
Do not use.
No connect - open pin.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
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Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
