168-pin Low Profile Registered SDRAM DIMMs
256MB, 512MB, 1GB
Preliminary Data Sheet
AC Characteristics (TA = 0°C to 70°C)
1. An initial pause of 200ms is required after power-up, then a Precharge All Banks command must be given followed by a minimum
of eight Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have V = 0.8V and V = 2.0V with the timing referenced to the VTT = 1.4V crossover point.
IL
IH
VTT
tT
VIH
VTT
VIL
Clock
Input
RT = 50 ohm
CLOAD = 50pF
tSETUP tHOLD
Z0 = 50 ohm
Output
tOH
tAC
tLZ
VTT
Output
AC Output Load Circuit
3. The transition time is measured between VIH and VIL (or between VIH and VIL).
4. AC measurements assume tT = 1ns.
5. In addition to meeting the transition rate specification, the clock and CKE must transition VIH and VIL (or between VIH and VIL) in
a monotonic manner.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
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Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
