CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Preliminary Data Sheet
Read and Write Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
-
Max
tAC3
tAC2
tOH3
tOH2
tLZ
Clock Access Time, CL = 3
Clock Access Time, CL = 2
Data Output Hold Time (CL=3)
Data Output Hold Time (CL=2)
Data Output to Low-Z Time
Data Output to High-Z Time (CL=2, 3)
Data Input Set-Up Time
4.5
ns
ns
1,2
1,2
-
4.5
2.7
2.7
1
-
ns
-
ns
-
ns
tHZ2
tDS
-
4.5
ns
3
4
1.5
0.8
13.3
4
-
-
-
-
-
-
ns
tDH
Data Input Hold Time
ns
tDPL
tDAL
tDQW
Data Input to Precharge
ns
Data Input to ACTV/Refresh
Data Write Mask Latency
CLK
CLK
CLK
0
tDQZ
DQM Data Output Disable Time
2
Notes:
1. Access time is measured at 1.4V (LVTTL) at max clock rate for the CAS latency specified. See AC Test Load.
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time.
3. Referenced to the time at which the output achieves an open circuit condition.
4. tDAL is equal to tDPL + tRP and can be less than 4 clocks if tDPL and tRP are both satisfied.
Refresh Parameters
Symbol
Parameter
-6.6
Units
Notes
Min
-
Max
64
-
tREF
Refresh Period
ms
ns
ns
1, 2
3
tSREX
Self Refresh Exit Time
Refresh Cycle Time
2CLK+tRC
60.0
tRFC
Notes:
1. 4096 cycles.
2. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.
3. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not
completed until tRC is satisfied once the Self-Refresh Exit command is registered.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 9 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
