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FM33256B-GTR 参数 Datasheet PDF下载

FM33256B-GTR图片预览
型号: FM33256B-GTR
PDF下载: 下载PDF文件 查看货源
内容描述: 3V集成处理器伴侣与F-RAM [3V Integrated Processor Companion with F-RAM]
分类和应用:
文件页数/大小: 29 页 / 620 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM33256B SPI Companion w/ FRAM  
Overview  
Processor Companion  
The FM33256B device combines a serial nonvolatile  
RAM with a real-time clock (RTC) and a processor  
companion. The companion is a highly integrated  
peripheral including a processor supervisor, analog  
comparator, a nonvolatile counter, and a serial  
In addition to nonvolatile RAM, the FM33256B  
incorporates a real-time clock with alarm and highly  
integrated processor companion. The companion  
includes a low-VDD reset, a programmable watchdog  
timer,  
a
16-bit nonvolatile event counter,  
a
number.  
The  
FM33256B  
integrates  
these  
comparator for early power-fail detection or other  
purposes, and a 64-bit serial number.  
complementary but distinct functions under  
a
common interface in a single package. The product is  
organized as two logical devices. The first is a  
memory and the second is the companion which  
includes all the remaining functions. From the system  
perspective they appear to be two separate devices  
with unique op-codes on the serial bus.  
Processor Supervisor  
Supervisors provide a host processor two basic  
functions: Detection of power supply fault conditions  
and a watchdog timer to escape a software lockup  
condition. The FM33256B has a reset pin (/RST) to  
drive a processor reset input during power faults,  
power-up, and software lockups. It is an open drain  
output with a weak internal pull-up to VDD. This  
allows other reset sources to be wire-OR’d to the  
/RST pin. When VDD is above the programmed trip  
point, /RST output is pulled weakly to VDD. If VDD  
drops below the reset trip point voltage level (VTP),  
the /RST pin will be driven low. It will remain low  
until VDD falls too low for circuit operation which is  
the VRST level. When VDD rises again above VTP,  
The memory is organized as a standalone nonvolatile  
SPI memory using standard op-codes. The real-time  
clock and supervisor functions are accessed under  
their own op-codes. The clock and supervisor  
functions are controlled by 30 special function  
registers. The RTC/alarm and some control registers  
are maintained by the power source on the VBAK  
pin, allowing them to operate from battery or backup  
capacitor power when VDD drops below a set  
threshold. Each functional block is described below.  
/RST continues to drive low for at least 50 ms (tRPU  
)
to ensure a robust system reset at a reliable VDD level.  
After tRPU has been met, the /RST pin will return to  
the weak high state. While /RST is asserted, serial  
bus activity is locked out even if a transaction  
occurred as VDD dropped below VTP. A memory  
operation started while VDD is above VTP will be  
completed internally.  
Memory Operation  
The FM33256B is available with 256Kb of memory.  
The device uses two-byte addressing for the memory  
portion of the chip. This makes the device software  
compatible with its standalone memory counterparts,  
such as the FM25W256.  
Table 1 below shows how bits VTP(1:0) control the  
trip point of the low-VDD reset. They are located in  
register 18h, bits 0 and 1. The reset pin will drive  
low when VDD is below the selected VTP voltage, and  
the SPI interface and F-RAM array will be locked  
out. Figure 2 illustrates the reset operation in  
Memory is organized in bytes. The 256Kb memory is  
32,768 x 8. The memory is based on F-RAM  
technology. Therefore it can be treated as RAM and  
is read or written at the speed of the SPI bus with no  
delays for write operations. It also offers effectively  
unlimited write endurance unlike other nonvolatile  
memory technologies. The SPI protocol is described  
on page 18.  
response to a low VDD  
.
VTP Setting VTP1 VTP0  
2.6V  
2.75V  
2.9V  
3.0V  
0
0
1
1
0
1
0
1
The memory array can be write-protected by  
software. Two bits (BP0, BP1) in the Status Register  
control the protection setting. Based on the setting,  
the protected addresses cannot be written. The Status  
Register & Write Protection is described in more  
detail on page 20.  
Table 1.  
This product conforms to specifications per the terms of the Ramtron  
standard warranty. The product has completed Ramtron’s internal  
qualification testing and has reached production status.  
Ramtron International Corporation  
1850 Ramtron Drive, Colorado Springs, CO 80921  
(800) 545-FRAM, (719) 481-7000  
www.ramtron.com  
Rev. 3.0  
Aug. 2012  
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