FM24C256
No
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
Data
1
P
By FM24C256
Acknowledge
Figure 7. Current Address Read
No
Acknowledge
Start
S
Address
Acknowledge
By Master
Stop
Slave Address
1
A
Data Byte
A
Data Byte
1 P
By FM24C256
Acknowledge
Data
Figure 8. Sequential Read
Start
No
Address
Acknowledge
Start
Address
By Master
Stop
S
Slave Address
0
A
Address MSB
A
Address LSB
Acknowledge
A
S
Slave Address
1
A
Data Byte
Data
1 P
By FM24C256
Figure 9. Selective (Random) Read
8 bytes per segment. Endurance can be optimized by
ensuring frequently accessed data is located in
different segments. Regardless, FRAM read and
write endurance is effectively unlimited at the 1MHz
two-wire speed. Even at 30 accesses per second to
the same segment, 10 years time will elapse before
10 billion endurance cycles occur.
Endurance
A FRAM internally operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each read and write access. The FRAM
architecture is based on an array of rows and
columns. Rows (A14-A6) are subdivided into 8
segments (A5-A3). Each access causes an endurance
cycle for a row segment. In the FM24C256, there are
Rev 3.1
May 2005
Page 7 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
