FM24C256
Addressing Overview
Write Operation
After the FM24C256 (as receiver) acknowledges the
device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB (upper byte).
Since the device uses only 15 address bits, the value
of the upper bits is a “don’t care”. Following the
MSB is the LSB (lower byte) with the remaining
eight address bits. The address value is latched
internally. Each access causes the latched address
value to be incremented automatically. The current
address is the value that is held in the latch, either a
newly written value or the address following the last
access. The current address will be held as long as
power remains or until a new value is written. Reads
always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the device address
to a 0. After addressing, the bus master sends each
byte of data to the memory and the memory
generates an acknowledge condition. Any number of
sequential bytes may be written. If the end of the
address range is reached internally, the address
counter will wrap from 7FFFh to 0000h.
Unlike other nonvolatile memory technologies,
there is essentially no write delay with FRAM.
Since the read and write access times of the
underlying memory are the same, the user
experiences no delay on the bus. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including a read or write
can occur immediately following
Acknowledge polling, technique used with
EEPROMs to determine if a write has completed is
a
write.
After transmission of each data byte, just prior to the
acknowledge, the FM24C256 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing externally.
After the last address (7FFFh) is reached, the address
latch will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
a
unnecessary and will always return
condition.
a ready
Internally, an actual memory write occurs after the
8th data bit is transferred. It will be complete before
the Acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using a Start or Stop
condition prior to the 8th data bit. The FM24C256
uses no page buffering.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24C256 can begin. For a read operation the
FM24C256 will place 8 data bits on the bus then wait
for an Acknowledge from the master. If the
Acknowledge occurs, the FM24C256 will transfer the
next sequential byte. If the Acknowledge is not sent,
the FM24C256 will end the read operation. For a
write operation, the FM24C256 will accept 8 data
bits from the master then send an acknowledge. All
data transfer occurs MSB (most significant bit) first.
The memory array can be write protected using the
WP pin. Pulling the WP pin high will write-protect
all addresses. The FM24C256 will not acknowledge
data bytes that are written when WP is active. In
addition, the address counter will not increment if
writes are attempted to these addresses. Setting WP
low will deactivate this feature. WP is internally
pulled down. The state of WP should remain stable
from the Start command until the address is
complete.
Memory Operation
The FM24C256 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C256 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Figure 5 and 6 below illustrate both a single-byte
and multiple-write.
Rev 3.1
May 2005
Page 5 of 12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
