Ramtron
FM1608
Figure 1. Block Diagram
A10-A12
Block Decoder
Pin
Description
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
Address
Latch
A0-A12
A0-A7
Row
Decoder
CE
A8-A9
Column Decoder
Control
Logic
WE
OE
DQ0-7
I/O Latch
Bus Driver
Pin Name
Pin Number
I/O Pin Description
A0-A12
2-10, 21, 23-25
I
Address. The 13 address lines select one of 8,192 bytes in the FRAM
array. The address value will be latched on the falling edge of /CE.
DQ0-7
/CE
11-13, 15-19
20
I/O Data. 8-bit bi-directional data bus for accessing the FRAM array.
I
Chip Enable. /CE selects the device when low. The falling edge of /CE
causes the address to be latched internally. Address changes that
occur after /CE goes low will be ignored until the next falling edge
occurs.
/OE
22
27
I
I
Output Enable. When /OE is low the FM1608 drives the data bus when
valid data is available. Taking /OE high causes the DQ pins to be tri-
stated.
/WE
Write Enable. Taking /WE low causes the FM1608 to write the contents
of the data bus to the address location latched by the falling edge of
/CE.
VDD
VSS
28
14
I
I
Supply Voltage. 5V
Ground.
Functional Truth Table
/CE
H
æ
/WE
X
X
H
L
/OE
X
X
L
X
Function
Standby/Precharge
Latch Address
Read
L
L
Write
28 July 2000
2/12
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
