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FM1110-QG 参数 Datasheet PDF下载

FM1110-QG图片预览
型号: FM1110-QG
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, PQCC16]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 8 页 / 286 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号FM1110-QG的Datasheet PDF文件第1页浏览型号FM1110-QG的Datasheet PDF文件第2页浏览型号FM1110-QG的Datasheet PDF文件第3页浏览型号FM1110-QG的Datasheet PDF文件第4页浏览型号FM1110-QG的Datasheet PDF文件第6页浏览型号FM1110-QG的Datasheet PDF文件第7页浏览型号FM1110-QG的Datasheet PDF文件第8页  
FM1110 NV Quad State Saver  
AC Parameters (TA = -40C to + 85C, VDD = 4.5V to 5.5V, CL = 30 pF unless otherwise specified)  
Symbol  
Parameter  
Min  
Max  
Units  
Notes  
fMAX  
tLOW  
tHIGH  
tPD  
Maximum Clock Frequency  
CLK Low Period  
CLK High Period  
Propagation delay CLK to QN  
EN Low to QN Hi-Z  
1
MHz  
s  
s  
ns  
0.3  
0.3  
50  
25  
tHZ  
ns  
1
1
1
tR  
tF  
Input Rise Time  
Input Fall Time  
100  
100  
ns  
ns  
tDS  
Data (DN) Setup Time to CLK   
Data (DN) Hold Time after CLK   
EN Hold Time (EN High after CLK )  
EN High Time  
5
10  
50  
5
ns  
ns  
ns  
s  
s  
tDH  
tEHD  
tEH  
-
tEL  
EN Low Time  
2
Notes  
1. This parameter is characterized but not tested.  
Power Cycling and Data Retention (TA = -40C to + 85C, VDD = 4.5V to 5.5esse spec)  
Symbol Parameter  
Nonvolatile Data Retention Time  
VDD Rise Time  
Min  
45  
50  
M
0.5  
-
U
ye
V  
s  
Notes  
tVDR  
tVDF  
1
1
2
VDD Fall me  
tRE
EN Rore Time  
EPower m
Eirst Clock K wer Up  
1
4
s  
s  
-
3
asuoint oDD waveform.  
wer n EN goes high the nonvolatile latches are read and the values restored to the outputs QN.  
3power up, this is the minimum time required before a state change operation may occur. EN and VDD may be  
coincident at power up, and in this case tEHFC time is referenced to VDD (min) and CLK .  
Capacitance (TA = 25C , f=1.0 MHz, VDD = 5.0V)  
Symbol Parameter  
CI Input Capacitance  
Notes  
Min  
-
Max  
14  
Units  
pF  
Notes  
1
1. This parameter is characterized but not tested.  
Rev. 4.0  
Oct 2012  
Page 5 of 8