FM1110 NV Quad State Saver
Block Diagram and Truth Table
INPUTS
EN CLK DN
OUTPUT
QN
D
Q
N
N
NV
State
Saver
CLK
EN
H
H
H
L
↑
↑
L
H
X
X
L
H
Q0
H or L
X
Hi-Z
L
H
X
↑
Low voltage level
High voltage level
Don’t Care
CLK rising edge
Q0 Previous output state before CLK ↑
Pin Descriptions
Pin Name
D(3:0)
Q(3:0)
CLK
I/O
Description
Data inputs
Data outputs
I
O
I
Clock: On a rising edge of CLK, the DN inputs are transferred to the QN outputs. While
CLK is high or low, the QN outputs do not change regardless of the state of the data
inputs. See truth table.
EN
I
Enable. This active-high input enables the device. When low, inputs are ignored and
updates to the nonvolatile cells are prevented. When high, the device operates
normally.
VDD
VSS
Supply Power Supply (4.5V to 5.5V)
Supply Ground
Rev. 4.0
Oct 2012
Page 2 of 8
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
