only specified on the /RE transition. During page mode burst write
operations, the same mask is used for all write operations.
Reduced Pin Count Operation
It is possible to simplify the interface to the 4MByte SIMM to
reduce the number of control lines. /RE and /RE could be tied
together externally to provide a single row enable2. W/R and /G can
be tied together if reads are not performed during write hit cycles.
This external wiring simplifies the interface without any
performance impact.
0
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles during which /S can be disabled.
Pin Descriptions
/RE — Row Enable
0,2
This input is used to initiate DRAM read and write operations
and latch a row address as well as the states of W/R and /F. It is not
necessary to clock /RE to read data from the EDRAM SRAM row
registers. On read operations, /RE can be brought high as soon as
data is loaded into cache to allow early precharge.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
/CAL0-3,P — Column Address Latch
/RE Only Refresh Operation
This input is used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address is closed and the output of the latch contains
the address present while /CAL was high. It also controls the
operation of the output data latch. Data is latched while /CAL is
high, and the latch is transparent when /CAL is low.
Although /F refresh using the internal refresh counter
is the recommended method of EDRAM refresh, it is
possible to perform an /RE only refresh using an
externally supplied row address. /RE refresh is performed
by executing a write cycle (W/R and /F are high) where /CAL is
not clocked. This is necessary so that the current cache contents
and LRR are not modified by the refresh operation. All
combinations of addresses A must be sequenced every 64ms
refresh period. A does not 0n-e9ed to be cycled. Read refresh cycles
W/R — Write/Read
10
This input along with /F specifies the type of DRAM operation
initiated on the low going edge of /RE. When /F is high, W/R
specifies either a write (logic high) or read operation (logic low).
are not allowed because a DRAM refresh cycle does not occur
when a read refresh address matches the LRR address latch.
+3.3 Volt Power Supply Operation
/F — Refresh
If the +3.3 volt power supply option is specified, the EDRAM
will operate from a +3.3 volt ±0.3 volt power supply and all inputs
and outputs will have LVTTL/LVCMOS compatible signal levels. The
+3.3 volt EDRAM will not accept input levels which exceed the
power supply voltage. If mixed I/O levels are expected in your
system, please specify the +5 volt version of the EDRAM.
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both /CAL and /WE are low.
Low Power Mode
/G — Output Enable
This input controls the gating of read data to the output data
pin during read operations.
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce standby
current.
/S — Chip Select
Low Power, Self-Refresh Option
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in its low power mode. /S
must remain active throughout any read or write operation. With
the exception of /F refresh cycles, /RE should never be clocked
when /S is inactive.
When the low power, self refresh mode option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this
mode, the power is turned off to all I/O pins except /RE to minimize
chip power, and an on-board refresh clock is enabled to perform
self-refresh cycles using the on-board refresh counter. The EDRAM
remains in this low power mode until /RE is brought high again to
terminate the mode. The EDRAM /RE input must remain high for tRP2
following exit from self-refresh mode to allow any on-going internal
refresh to terminate prior to the next memory operation.
DQ0-35 — Data Input/Output
These bidirectional data pins are used to read and write data
to the EDRAM. On the DM2252 write-per-bit memory, these pins
are also used to specify the bit mask used during write operations.
A
0-10 — Multiplex Address
Initialization Cycles
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 9-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
A minimum of eight /RE active initialization cycles (read, write
or refresh)are required before normal operation is guaranteed.
Following these start-up cycles, two read cycles to different row
addresses must be performed for each of the four internal banks
of DRAM to initialize the internal cache logic. Row address bits A
and A define the four internal DRAM banks. /RE must be high fo2r V Power Supply
9
CC These inputs are connected to the +5 or 3.3 volt power supply.
300ns prior to initialization.
V Ground
Unallowed Mode
Read, write, or /RE only refresh operations must not be initiated
to unselected memory banks by clocking /RE when /S is high.
SS
These inputs are connected to the power supply ground
connection.
2-78
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
