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DM1M36SJ7-15I 参数 Datasheet PDF下载

DM1M36SJ7-15I图片预览
型号: DM1M36SJ7-15I
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 1MX36, 15ns, CMOS, PSMA72]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 19 页 / 188 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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Electrical Characteristics  
T = 0 - 70°C (Commercial), -40 to 85°C (Industrial)  
A
3.3V Option  
Symbol  
Parameters  
Supply Voltage  
Max  
Min  
Test Conditions  
Max  
3.6V  
Min  
V
3.0V  
4.75V  
5.25V  
Vcc+0.5V  
0.8V  
All Voltages Referenced to V  
SS  
CC  
V
Input High Voltage  
Input Low Voltage  
Output High Level  
Output Low Level  
2.0V  
Vss-0.3V  
2.4V  
V +0.3V 2.4V  
IH  
CC  
V
0.8V Vss-0.5V  
2.4V  
IL  
VOH  
VOL  
Ii(L)  
IOUT = - 5mA (-2ma For 3.3 Volt Option)  
IOUT = 4.2mA (2ma For 3.3 Volt Option)  
0.4V  
0.4V  
90µA  
90µA  
Input Leakage Current  
Output Leakage Current  
-45µA  
-45µA  
45µA  
45µA  
-90µA  
-90µA  
OV V Vcc + 0.5 Volts  
IN  
IO(L)  
O VI/O Vcc  
Operating Current — DM1M32SJ  
33MHz Typ(1)  
880mA  
-15 Max  
Symbol  
Operating Current  
Random Read  
-12 Max  
Test Condition  
Notes  
I
1800mA 1440mA /RE, /CAL, /G and Addresses Cycling: t = t Minimum  
2, 3  
CC1  
C
C
I
Fast Page Mode Read  
Static Column Read  
Random Write  
520mA  
1160mA  
880mA  
920mA /CAL, /G and Addresses Cycling: t = t Minimum  
2, 4  
2, 4  
2, 3  
2, 4  
PC PC  
CC2  
I
440mA  
1080mA  
400mA  
8mA  
720mA  
/G and Addresses Cycling: t = t Minimum  
SC SC  
CC3  
I
1520mA  
/RE, /CAL, /WE and Addresses Cycling: t = t Minimum  
1200mA  
C
C
CC4  
I
Fast Page Mode Write  
1080mA 840mA  
/CAL, /WE and Addresses Cycling: t = t Minimum  
PC PC  
CC5  
I
Standby  
8mA  
8mA  
All Control Inputs Stable  
/S, /F, W/R, /WE and A  
V
- 0.2V  
CC6  
CC  
at  
V -0.2V,  
CC  
I
0-10  
Self-Refresh (-L Option)  
1.6mA  
1.6mA  
1.6mA  
CC7  
/RE and /CAL at  
V
<
+ 0.2V, I/O Open  
SS  
I
1
Average Typical  
Operating Current  
240mA  
See "Estimating EDRAM Operating Power" Application Note  
CCT  
Operating Current — DM1M36SJ  
Symbol  
Operating Current  
Random Read  
33MHz Typ (1)  
990mA  
-15 Max  
-12 Max  
Test Condition  
Notes  
ICC1  
2025mA 1620mA /RE, /CAL, and Addresses Cycling: tC = tC Minimum  
1305mA 1035mA /CAL and Addresses Cycling: tPC = tPC Minimum  
2, 3, 5  
ICC2  
ICC3  
ICC4  
ICC5  
ICC6  
ICC7  
Fast Page Mode Read  
Static Column Read  
Random Write  
585mA  
2, 4, 5  
2, 4, 5  
2, 3  
495mA  
1215mA  
450mA  
9mA  
990mA  
810mA Addresses Cycling: tSC = tSC Minimum  
/RE, /CAL, /WE, and Addresses Cycling: tC = tC Minimum  
1710mA  
1350mA  
Fast Page Mode Write  
1215mA 945mA /CAL, /WE, and Addresses Cycling: tPC = tPC Minimum  
2, 4  
9mA  
9mA  
Standby  
All Control Inputs Stable VCC - 0.2V, Output Driven  
Self-Refresh  
Option (-L)  
/S, /F, W/R, /WE, and A0-10 at VCC - 0.2V  
/RE and /CAL at VSS + 0.2V, I/O Open  
1.8mA  
270mA  
1.8mA  
1.8mA  
ICCT  
1
Average Typical  
See “Estimating EDRAM Operating Power” Application Note  
Operating Current  
(1) “33MHz Typ” refers to worst case I expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested  
CC  
or guaranteed. (2) I is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) I is measured with a maximum of one address change while  
CC  
CC  
/RE = V . (4) I is measured with a maximum of one address change while /CAL = V . (5) /G is high.  
IL  
CC  
IH  
2-82