the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (tRAH + tASC for
the column address and tDS for the data). During a write burst
sequence, the second write data can be posted at time tRSW after
/RE. Subsequent writes within a page can occur with write cycle
time tPC. During a write miss sequence, cache reads are inhibited
and the output buffers are disabled (independently of /G) until
time tWRR after /RE goes high. At the end of a write sequence (after
/CAL and /WE are brought high and tRE is satisfied), /RE can be
brought high to precharge the memory. It is possible to perform
cache reads concurrently with the precharge. During write
sequences, a write operation is not performed unless both /CAL
and /WE are low. As a result, /CAL can be used as a byte write select
in multi-chip systems. If /CAL is not clocked on a write sequence,
the memory will perform a /RE only refresh to the selected row and
data will remain unmodified.
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
W/E, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A (LRR: a 9-bit row address latch for each internal
2,9
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
address and data are posted to the DRAM as soon as the column
address is latched by bringing /CAL low and the write data is
latched by bringing /WE low (both /CAL and /WE must be high
when initiating the write cycle with the falling edge of /RE). The
write address and data can be latched very quickly after the fall of
/RE (tRAH + tASC for the column address and tDS for the data).
During a write burst sequence, the second write data can be posted
at time tRSW after /RE. Subsequent writes within a page can occur
with write cycle time tPC. With /G enabled and /WE disabled, it is
possible to perform cache read operations while the /RE is
activated in write hit mode. This allows read-modify-write, write-
verify, or random read-write sequences within the page with 12ns
cycle times (the first read cannot complete until after time tRAC2).
At the end of a write sequence (after /CAL and /WE are brought
high and tRE is satisfied), /RE can be brought high to precharge the
memory. It is possible to perform cache reads concurrently with
precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low. As a result, the /CAL
input can be used as a byte write select in multi-chip systems. If /CAL
is not clocked on a write sequence, the memory will perform a /RE only
/RE Inactive Operation
It is possible to read data from the SRAM cache without
clocking /RE. This option is desirable when the external control
logic is capable of fast hit/miss comparison. In this case, the
controller can avoid the time required to perform row/column
multiplexing on hit cycles. This capability also allows the EDRAM to
perform cache read operations during precharge and refresh
cycles to minimize wait states. It is only necessary to select /S and
/G and provide the appropriate column address to read data. The
row address of the SRAM cache accessed without clocking /RE will
be specified by the LRR address latch loaded during the last /RE
active read cycle. To perform a cache read, /CAL is clocked to latch the
column address. The cache data is valid at time tCLV after the column
address is setup to /CAL.
refresh to the selected row and data will remain unmodified
.
DRAM Write Miss
Write-Per-Bit Operation
A DRAM write request is initiated by clocking /RE while W/R,
W/E, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
The DM1M36SJ6 EDRAM SIMM provides a write-per-bit
capability to selectively modify individual parity bits (DQ
)
8,17,26,35
for byte write operations. The parity device (DM2252) is selected
via /CAL . Data bits do not require or support write-per-bit
capabilitPy. Byte write selection to non-parity bits is accomplished
address bits A (LRR: a 9-bit row address latch for each internal
2,9
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified.The write address
and data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
via /CAL . The bits to be written are determined by a bit mask data
0-3
word which is placed on the parity I/O data pins prior to clocking
/RE. The logic one bits in the mask data select the bits to be
written. As soon as the mask is latched by /RE, the mask data is
removed and write data can be placed on the databus. The mask is
EDRAM Basic Operating Modes
Function
/CAL /WE
A
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
/F
H
H
H
H
L
/S
L
/RE
↓
W/R
L
0-10
Read Hit
H
H
H
H
X
H
X
X
X
H
H
X
H
X
Row = LRR
Read Miss
Row ≠ LRR
L
↓
L
Write Hit
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
L
↓
H
Write Miss
Row ≠ LRR
L
↓
H
Internal Refresh
Low Power Standby
Unallowed Mode
X
X
X
X
H
H
↓
X
Standby Current
H
L
X
X
H
Unallowed Mode (Except -L Option)
X
Low Power Self
Refresh Option
Standby Current, Internal Refresh Clock
L
H
X
H
↓
X
H
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
2-77
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
