P4C1049
AC TEST CONDITIONS
TRUTH TABLE
InputPulseLevels
GND to 3.0V
Mode
Standby
Standby
CE OE W E
I/O
High Z
High Z
Power
Standby
Standby
Input Rise and Fall Times
InputTimingReferenceLevel
OutputTimingReferenceLevel
OutputLoad
3ns
1.5V
1.5V
H
X
X
X
X
X
High Z
Active
DOUT Disabled
L
H
H
See Figures 1 and 2
L
L
H
L
DOUT
High Z
Active
Active
L
X
Read
Write
Figure 1. Output Load
Figure2. TheveninEquivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1049, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM128 REV OR
Page 8 of 12
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