P4C1026
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Mode
CE OE W E
I/O
Power
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
Standby
H
X
X
HighZ
Standby
DOUT
Disabled
L
L
L
H
L
H
H
L
HighZ
DOUT
Active
Active
Active
1.5V
Read
Write
See Figures 1 and 2
X
HighZ
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Because of the ultra-high speed of the P4C1258, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
Document # SRAM127 REV E
Page 6 of 10
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