P4C1026
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
Sym.
Parameter
Unit
Min Max Min Max Min Max Min
Max
tWC
tCW
tAW
Write Cycle Time
13
12
20
15
25
18
35
25
ns
ns
Chip Enable Time to End of Write
Address Valid to End of Write
AddressSet-upTime
18
0
12
0
15
0
25
0
ns
ns
ns
tAS
tWP
tAH
18
Write Pulse Width
12
15
25
Address Hold Time from End of Write
0
7
0
0
8
0
0
10
0
0
15
0
ns
ns
ns
ns
ns
tDW
tDH
tWZ
tDW
Data Valid to End of Write
DataHoldTime
Write Enable to Output in High Z
6
8
10
15
Output Active from End of Write
2
2
2
3
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM127 REV E
Page 5 of10
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