欢迎访问ic37.com |
会员登录 免费注册
发布采购

P4C1026-25J4C 参数 Datasheet PDF下载

P4C1026-25J4C图片预览
型号: P4C1026-25J4C
PDF下载: 下载PDF文件 查看货源
内容描述: 超高速256K ×4的静态CMOS RAM [ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM]
分类和应用:
文件页数/大小: 10 页 / 290 K
品牌: PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
 浏览型号P4C1026-25J4C的Datasheet PDF文件第1页浏览型号P4C1026-25J4C的Datasheet PDF文件第2页浏览型号P4C1026-25J4C的Datasheet PDF文件第3页浏览型号P4C1026-25J4C的Datasheet PDF文件第5页浏览型号P4C1026-25J4C的Datasheet PDF文件第6页浏览型号P4C1026-25J4C的Datasheet PDF文件第7页浏览型号P4C1026-25J4C的Datasheet PDF文件第8页浏览型号P4C1026-25J4C的Datasheet PDF文件第9页  
P4C1026  
AC CHARACTERISTICS—READ CYCLE  
(VCC = 5V ± 10%, All Temperature Ranges)(2)  
-25  
-15  
-35  
-20  
Sym.  
Parameter  
Unit  
Max  
Min  
Min Max  
Min Max  
Min Max  
tRC  
tAA  
tAC  
tOH  
ReadCycleTime  
35  
25  
25  
25  
2
ns  
ns  
15  
20  
20  
Address Access Time  
15  
15  
35  
20  
35  
ns  
ns  
Chip Enable Access Time  
2
2
2
2
3
OutputHoldfromAddressChange  
ns  
3
3
tLZ  
Chip Enable to Output in Low Z  
Chip Disable to Output in High Z  
Chip Enable to Power Up Time  
Chip Disable to Power Down Time  
tHZ  
ns  
ns  
11  
10  
8
9
0
0
0
tPU  
tPD  
0
ns  
35  
25  
15  
20  
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)  
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)  
Notes:  
1. Stresses greater than those listed under MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification  
is not implied. Exposure to MAXIMUM rating conditions for extended  
periods may affect reliability.  
2. Extended temperature operation guaranteed with 400 linear feet per  
minute of air flow.  
3. Transient inputs with VIL and IIL not more negative than –3.0V and  
–100mA, respectively, are permissible for pulse widths up to 20ns.  
4. This parameter is sampled and not 100% tested.  
5. WE is HIGH for READ cycle.  
6. CE is LOW and OE is LOW for READ cycle.  
7. ADDRESSmustbevalidpriorto,orcoincidentwithCE transitionLOW.  
8. Transition is measured ± 200 mV from steady state voltage prior to  
change, with loading as specified in Figure 1. This parameter is  
sampled and not 100% tested.  
9. Read Cycle Time is measured from the last valid address to the first  
transitioning address.  
Document # SRAM127 REV E  
Page 4 of 10