P4C1024
TIMING WAVEFORM OF WRITE CꢁCLE NO. 2 (CE CONTROLLED)(11)
TRUTH TABLE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
Mode
CE1 CE2 OE WE I/O
Power
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
H
ꢀ
ꢀ
High Z
High Z
Standby
Standby
ꢀ
ꢀ
ꢀ
Standby
Standby
1.5V
ꢀ
L
1.5V
L
H
H
H
High Z Active
DOUT Disabled
See Fig. 1 and 2
DOUT
L
L
H
H
L
H
L
Read
Write
Active
ꢀ
High Z Active
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
To avoid signal reflections, proper termination must be used; for ex-
ample, a 50Ω test environment should be terminated into a 50Ω load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω
resistor must be used in series with DOUT to match 166Ω (Thevenin
Resistance).
Becauseoftheultra-highspeedoftheP4C1024,caremustbetaken
when testing this device; an inadequate setup can cause a normal
functioningparttoberejectedasfaulty. Longhigh-inductanceleads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
Document # SRAM124 REV C
Page 7 of 14
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
