P4C1024
TIMING WAVEFORM OF READ CꢁCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CꢁCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CꢁCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
Notes:
5. WE is HIGH for READ cycle.
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW and CE2 transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
Document # SRAM124 REV C
Page 5 of 14
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
