P3C1256
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)
AC TEST CONDITIONS
TRUTH TABLE
Mode
CE
OE WE
I/O
Power
Input Pulse Levels
GND to 3.0V
Standby
X
X
Standby
H
X
L
High Z
High Z
High Z
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
Standby
X
H
X
H
Standby
Active
DOUT Disabled
1.5V
Read
Write
L
L
H
L
DOUT
L
Active
Active
See Figures 1 and 2
High Z
X
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P3C1256, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM122 REV B
Page 6 of 10
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