P3C1256L - 32K x 8 STATIC CMOS RAM
TIMIꢀꢂ WAVEFORM OF WRITE CꢄCLE ꢀO. 2 (CE COꢀTROLLED)(10)
AC TEST COꢀDITIOꢀS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Mode
CE
OE
ꢀ
WE
ꢀ
I/O
Power
Standby
Standby
Active
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
Standby
Standby
DOUT Disabled
Read
H
ꢀ
L
L
L
High Z
High Z
High Z
DOUT
ꢀ
ꢀ
1.5V
H
L
H
See Figures 1 and 2
H
Active
Write
ꢀ
L
High Z
Active
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
ꢀote:
Because of the high speed of the P3C1256L, care must be taken when
testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at
the comparator input, and a 589Ω resistor must be used in series with
DOUT to match 639Ω (Thevenin Resistance).
Document # SRAM143 REV A
Page 6
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
