February 2007
rev 1.4
ASM3P2508A
57 (H). To put ASM3P2508A in ‘power down’ mode, the
bit 1 of Byte 0 is to be changed to logic ‘0’. Hence writing a
55 (H) via I2C into Byte 0 would put the device in partial
‘power down’ mode where the PLL block generating
72 MHz / 48 MHz would be powered down while I2C block,
crystal oscillator, and the PLL block generating 120 MHz
would still be active. The organization of the register bits is
as below:
An example of a Byte Write via I2C to partially ‘power
down’ the device:
ASM3P2508A can be partially ‘powered down’ using bit 1
of Byte 0. The organization of the register bits for Byte ‘0’ is
given with default values below:
Bit
Bit
7
6
5
4
3
2
1
PLL2
Enable Enable
0
PLL1
7
6
5
4
3
2
1
PLL2
0
PLL1
Resv Resv Resv
Resv Resv Resv
Resv Resv Resv
Resv Resv Resv
Enable Enable
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
The function of partial power down of the device is of
interest to us - that is bit 1 of Byte 0. In the default mode
this bit is logic ‘1’. As such, the Byte 0 default value is
Byte 0
Byte 1
3F(H)
BF(H)
3F(H)
BF(H)
FOUT1CLK (MHz)
FOUT2CLK(MHz)
Power up default
48_MHz Mode
Power down PLL with 72MHz
Power down PLL with 48MHz
6F(H)
6F(H)
6D(H)
6D(H)
120
120
120
120
72
48
-
-
Figure showing a complete data transfer:
.
Peak EMI Reducing Solution
6 of 9
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
